Hierarchical overlapped tiling

Zhou, Xing; Giacalone, Jean‐Pierre; Garzarán, María Jesús; Kuhn, Robert H.; Ni, Yang; Padua, David

doi:10.1145/2259016.2259044

Cited by 64 publications

(33 citation statements)

References 35 publications

(38 reference statements)

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“…[4] describes the implementation of a page coloring framework in the Linux kernel. Apart from cache partitioning, researchers tried to increase the the shared cache utilization by employing compiler transformations and most commonly loop tiling transformations [6] [7] [5] [13] [14]. [6] describes a method for automatically generating multilevel tiled code for any polyhedral iteration space.…”

Section: Related Workmentioning

confidence: 99%

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management

Kelefouras

Κεραμίδας

Voros

2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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Abstract-In this paper, we present a new methodology that provides i) a theoretical analysis of the two most commonly used approaches for effective shared cache management (i.e., cache partitioning and loop tiling) and ii) a unified framework to fine tuning those two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by one order of magnitude keeping at the same time the number of arithmetical/addressing instructions in a minimal level. We also present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.

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Section: Related Workmentioning

confidence: 99%

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management

Kelefouras

Κεραμίδας

Voros

2017

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…techniques like cache oblivious, time skewing, wavefront or overlapped tiling [1][2][3][4][5][6][7][8][9][10][11][12]38]. In addition, domain-specific compilers have recently been developed for parallel code generation from a stylized stencil specification [39][40][41] or from a code excerpt [42].…”

Section: Related Workmentioning

confidence: 99%

“…Most prior work on optimizing stencil computations focus on lower-order methods (typically p = 2) where there is limited reuse of data and computations are notoriously memory bound. Much of this prior work reduces the amount of data movement by fusing multiple stencil sweeps through techniques like cache oblivious, time skewing, wavefront or overlapped tiling [1][2][3][4][5][6][7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Compiler-Directed Transformation for Higher-Order Stencils

Basu

Hall

Williams

et al. 2015

2015 IEEE International Parallel and Distributed Processing Symposium

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Abstract-As the cost of data movement increasingly dominates performance, developers of finite-volume and finite-difference solutions for partial differential equations (PDEs) are exploring novel higher-order stencils that increase numerical accuracy and computational intensity. This paper describes a new compiler reordering transformation applied to stencil operators that performs partial sums in buffers, and reuses the partial sums in computing multiple results. This optimization has multiple effects on improving stencil performance that are particularly important to higher-order stencils: exploits data reuse, reduces floating-point operations, and exposes efficient SIMD parallelism to backend compilers. We study the benefit of this optimization in the context of Geometric Multigrid (GMG), a widely used method to solve PDEs, using four different Jacobi smoothers built from 7-, 13-, 27-and 125-point stencils. We quantify performance, speedup, and numerical accuracy, and use the Roofline model to qualify our results. Ultimately, we obtain over 4× speedup on the smoothers themselves and up to a 3× speedup on the multigrid solver. Finally, we demonstrate that high-order multigrid solvers have the potential of reducing total data movement and energy by several orders of magnitude.

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“…(In the iterated stencil computation literature, the redundant regions are often called "ghost zones," and this strategy is sometimes called "overlapped tiling" [17,31].) On a modern x86, this strategy is 10× faster than the breadth-first strategy using the same amount of multithreaded and vector parallelism.…”

Section: Motivation: Scheduling a Two-stage Pipelinementioning

confidence: 99%

Halide

et al. 2013

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Image processing pipelines combine the challenges of stencil computations and stream programs. They are composed of large graphs of different stencil stages, as well as complex reductions, and stages with global or data-dependent access patterns. Because of their complex structure, the performance difference between a naive implementation of a pipeline and an optimized one is often an order of magnitude. Efficient implementations require optimization of both parallelism and locality, but due to the nature of stencils, there is a fundamental tension between parallelism, locality, and introducing redundant recomputation of shared values.We present a systematic model of the tradeoff space fundamental to stencil pipelines, a schedule representation which describes concrete points in this space for each stage in an image processing pipeline, and an optimizing compiler for the Halide image processing language that synthesizes high performance implementations from a Halide algorithm and a schedule. Combining this compiler with stochastic search over the space of schedules enables terse, composable programs to achieve state-of-the-art performance on a wide range of real image processing pipelines, and across different hardware architectures, including multicores with SIMD, and heterogeneous CPU+GPU execution. From simple Halide programs written in a few hours, we demonstrate performance up to 5× faster than hand-tuned C, intrinsics, and CUDA implementations optimized by experts over weeks or months, for image processing applications beyond the reach of past automatic compilers.

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Hierarchical overlapped tiling

Cited by 64 publications

References 35 publications

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management

Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management

Compiler-Directed Transformation for Higher-Order Stencils

Halide

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