Hierarchical Multipartite Function Evaluation

Abstract

Function evaluation is an important arithmetic computation in many signal processing applications, such as special function units in modern graphics processing units (GPUs). Hardware implementations of function evaluation usually consists of lookup tables (LUT) and some simple arithmetic units of multipliers and/or adders. LUT usually takes a significant portion of total area cost, especially when function evaluators are allowed to compute several different arithmetic functions with shared arithmetic units where evaluation of each function needs separate LUT. In this paper, we focus on the category of table-addition (TA) function evaluators that are composed of two types of LUT, table of initial values (TI) and table of offset values (TO), followed by a multi-operand adder. It has been shown that multipartite table method (MP) has significant improvement over prior similar designs such as symmetric bipartite table methods (SBTM) and symmetric table addition methods (STAM) for applications with low-to-medium precision requirements. This paper presents an extension of MP, called hierarchical multipartite (HMP), which further reduces total table size by applying several levels of table decompositions. Furthermore, we perform the bit-width optimization by jointly considering the impacts of all error sources during the search of best table decompositions, leading to more efficient hardware design. Besides, a new lossless decomposition of TI is presented, resulting in additional saving of table size without incurring any extra errors. Experimental results show that the proposed design can efficiently reduce the total area cost in ASIC and FPGA implementations.

Elementary Functions and Approximate Computing

“…Later on, De Dinechin and Tisserand improved these multipartite methods [64] and made them very attractive. A recent analysis of that class of algorithms and a new variant called hierarchical multipartite methods are presented by Hsiao et al in [65].…”

Lossless Differential Table Compression for Hardware Function Evaluation

“…This suggests that a further optimization is possible (these systematic zeroes should themselves be somehow compressed). The solution proposed in [7] is to add, to each entry of T d , the value of the w R − w L least significant bits (LSB) of the corresponding T ss entry. Thus, these bits can be removed from T ss , reducing its output size by w R − w L bits.…”

“…The refinement introduced in the present paper attempts to avoid this T d overflow bit. Instead of always removing the maximum number of output bits from T ss as in [7], we consider leaving some of these bits, in the hope that it allows to avoid the overflow bit in T d . If k extra output bits in T ss allows for a T d without overflow, the extra cost is k × 2 s bits and the benefit is 2 w A bits, so there is a potential net gain in storage.…”

“…For larger precisions, many evaluation methods may be used [1], [2]. These methods often rely on tables of precomputed values [3], [4], [5], [6], [7], [8]. These table-based methods expose a trade-off between storage and computation.…”

“…Hsiao et al introduced [6] then improved [7] a technique for compressing one specific table appearing in multipartite table methods [3]. This lossless differential table compression (LDTC) replaces one table with two smaller tables and an addition (Fig.…”