Hierarchical Domain Structure and Extremely Large Wall Current in Epitaxial BiFeO₃ Thin Films

Abstract

Erasable electrical conductive domain walls in an insulating ferroelectric matrix provide novel functionalities for applications in logic and memory devices. The crux of such success requires sufficiently high wall currents to drive high-speed and high-power nanodevices. This work provides an appealing strategy to increase the current by two orders of magnitude through the careful selection of current flowing paths along the charged walls. The dense walls come into form through the hierarchical evolution of the 71°, 109°, and 180° domains of epitaxial BiFeO 3 films in a planar-geometry ferroelectric resistance-switching memory cell. The engineered films grown on SrTiO 3 and GdScO 3 substrates allow the observation of detailed local configurations and the evolution of the different domain types using vector piezo-force microscopy. The higher local electrical conductivity near the charged domain walls is identified by conductive atomic-force microscopy. It is shown that 180° domain reversal proceeds by three-step 71° rotations of the pristine domains. Surprisingly, a maximum current of ≈300 nA is observed for current paths along charge-uncompensated head-to-head hierarchical domain walls connecting the two electrodes on the film surface. Furthermore, the achievable current level can be conveniently controlled by varying the relative directions of the initial polarization and the applied field.

The Observation of Domain‐Wall Current Transients Along with Charge Injection at Elevated Temperatures

“…The “on” current can be fitted using I ∝ V n power law, where n = 4.1, as indicated by the red dashed line in Figure b. The n value is much higher than 2 in the space–charge–limited current (SCLC) model . Therefore, the DW current decays quickly during backward sweeping of the I – V curve from +6 V to 0.…”

“…To further clarify the underlying physics of the charge injection phenomenon, the I – V curves with different sweeping speeds by changing the stressing interval time at each voltage point for the device with gap w / l of 1000/350 nm were measured at 408 K. The DW current reduces significantly with lower sweeping rate until to vanish at 210 ms, as shown in Figure b. The carrier transport across the DWs can be quantitatively modeled as a field‐effect current with a threshold voltage V T , which approximately equals the coercive voltage inferred from the I – V curve in 10 ms‐stressing time. The divergent polarization charges near the walls can be compensated by the captured electrons in the bulk region of the film (the fitting details are shown in the Supporting Information).…”

“…In addition, the DW currents in other ferroelectrics, for example, BaTiO 3 , LiNbO 3 , and Pb(Zr,Ti)O 3 , also underscore the defect‐related conduction behavior. Therefore, an in‐depth study of time‐dependent charge compensation behavior at the DW regions would be very helpful to understand the underlying physics of the wall conduction for the widened DW application in nanodevices, especially for the conduction enhancement in charged domain configuration …”

Next-generation ferroelectric domain-wall memories: principle and architecture

“…2b (left panel) shows an in-plane PFM phase image of two switched head-tohead 71°triangular domains in a (001) BiFeO 3 thin film, 16 where the in-plane polarization (P) intersects with E at an angle of α. 17 The concomitant CAFM image presented in the inset shows the significantly higher electrical conductivity of the entire domain-wall region. The wall current increases nonlinearly with the reduction in the gap length to follow a space-charge-limited conduction process with a thermal activation energy of 0.16 eV; 16 the current increases exponentially with the value of sin α (0°≤ α ≤ 90°), and the wall current is more than 300 nA with α = 90°.…”

“…The wall current increases nonlinearly with the reduction in the gap length to follow a space-charge-limited conduction process with a thermal activation energy of 0.16 eV; 16 the current increases exponentially with the value of sin α (0°≤ α ≤ 90°), and the wall current is more than 300 nA with α = 90°. 17 Once the switching pulse is removed, domain backswitching occurs and erases the walls within a time as short as 16 ns. 16 This temporary domain nature permits the nondestructive reading of nanodomain information while also avoiding long-term defect accumulation at the persistent walls.…”