Hierarchical and reconfigurable optical/electrical interconnection network for high-performance computing

Abstract

Compared with electrical packet switches, optical switching technology could enable a more desirable high-performance computing (HPC) system with lower power consumption, lower delay, higher bandwidth, and more flexibility. In this article, we designed a hierarchical and reconfigurable optical/electrical HPC interconnection network. The traffic matrix of the target task can be decomposed into multiple matrix groups that are executed in parallel, and the network topology in each layer can be reconfigured according to the subtraffic matrix associated with this layer. For interlayer cross-connection, we use a shuffle network to offer a direct optical bypass for a huge aggregated amount of interlayer communication requirements, as well as multiple light paths. We propose a reconfiguration optimization algorithm and routing algorithm to optimize network performance. Simulation results show that, with the proposed architecture and algorithms, the average path length per unit of communication intensity is minimized by 13.7%–52.4%, the delay is reduced by more than 14.8%, and throughput is improved by 33% at least compared with Mesh, Torus, and Dragonfly.

English Language Features in Linguistics by High-Performance Computing

“…Parallel computing is synonymous with supercomputing and high-performance computing, and is one of the important directions in the development of computer technology [12]. Figure 2 is a diagram of the parallel solution process of the problem.…”