Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems

Park, Jongkil; Yu, Ting; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

doi:10.1109/tnnls.2016.2572164

Cited by 106 publications

(75 citation statements)

References 54 publications

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“…We refer to this as a single NSAT tile. Note that such tiled architecture has been proposed earlier in the context of neuromorphic hardware with multi-tile communication enabled through a hierarchical AER communication fabric (Park et al, 2017). The contribution of this work therefore focused on specifics of the digital implementation inside each tile.…”

Section: Methodsmentioning

confidence: 99%

“…Extreme efficiency in data-driven autonomy hinges on the establishment of (i) energy-efficient computational building blocks and (ii) algorithms that build on these blocks. NSAT is a spiking neural network architecture designed on these assumptions, using neural building blocks that are constructed from algorithmic principles and an event-based architecture that emphasizes locally dense and globally sparse communication (Park et al, 2017). …”

Section: Introductionmentioning

confidence: 99%

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Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning

et al. 2018

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Embedded, continual learning for autonomous and adaptive behavior is a key application of neuromorphic hardware. However, neuromorphic implementations of embedded learning at large scales that are both flexible and efficient have been hindered by a lack of a suitable algorithmic framework. As a result, most neuromorphic hardware are trained off-line on large clusters of dedicated processors or GPUs and transferred post hoc to the device. We address this by introducing the neural and synaptic array transceiver (NSAT), a neuromorphic computational framework facilitating flexible and efficient embedded learning by matching algorithmic requirements and neural and synaptic dynamics. NSAT supports event-driven supervised, unsupervised and reinforcement learning algorithms including deep learning. We demonstrate the NSAT in a wide range of tasks, including the simulation of Mihalas-Niebur neuron, dynamic neural fields, event-driven random back-propagation for event-based deep learning, event-based contrastive divergence for unsupervised learning, and voltage-based learning rules for sequence learning. We anticipate that this contribution will establish the foundation for a new generation of devices enabling adaptive mobile systems, wearable devices, and robots with data-driven autonomy.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning

et al. 2018

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“…no dedicated access to a stored mapping table). This contrasts with Neurogrid [25] and HiAER [23], which achieve low-cost largescale routing at the expense of requiring external mapping table storage, thus indirectly inducing high resource and power overheads. SpiNNaker [24], [35] embeds the largest-scale multicast connectivity infrastructure proposed so far.…”

Section: A Hierarchical Event Routingmentioning

confidence: 99%

“…The latter aspect can be mitigated by a controller update, similarly to the crossbar optimization with start and end addresses proposed in Section IV-C for fully-connected layers. Finally, it is worth noting that all the routers in the aforementioned approaches operate asynchronously, except in HiAER [23] and MorphIC. In MorphIC, the choice of clocked operation for the routers allows for a straightforward design at the expense of efficiency.…”

Section: A Hierarchical Event Routingmentioning

confidence: 99%

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning

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2019

IEEE Trans. Biomed. Circuits Syst.

133

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Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource-and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse eventbased data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power-and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage onchip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quadcore binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm 2 in 65nm CMOS, achieving a high density of 738k synapses/mm 2 . MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.

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“…On a platform supporting only spike-based communication, this information must be encoded in spikes. On the other hand, dashed edges crossing domains can be handled through efficient address-event communication protocols, such as in hierarchical AER (HiAER) (Park et al., 2017). In this example, the synthesized learning subgraph (red nodes and edges) is consistent with eRBP, via a random matrix G 0 .…”

Section: Distilling Machine Learning and Neuroscience For Neuromorphimentioning

confidence: 99%

Data and Power Efficient Intelligence with Neuromorphic Learning Machines

Neftci

2018

iScience

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The success of deep networks and recent industry involvement in brain-inspired computing is igniting a widespread interest in neuromorphic hardware that emulates the biological processes of the brain on an electronic substrate. This review explores interdisciplinary approaches anchored in machine learning theory that enable the applicability of neuromorphic technologies to real-world, human-centric tasks. We find that (1) recent work in binary deep networks and approximate gradient descent learning are strikingly compatible with a neuromorphic substrate; (2) where real-time adaptability and autonomy are necessary, neuromorphic technologies can achieve significant advantages over main-stream ones; and (3) challenges in memory technologies, compounded by a tradition of bottom-up approaches in the field, block the road to major breakthroughs. We suggest that a neuromorphic learning framework, tuned specifically for the spatial and temporal constraints of the neuromorphic substrate, will help guiding hardware algorithm co-design and deploying neuromorphic hardware for proactive learning of real-world data.

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Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems

Cited by 106 publications

References 54 publications

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning

Data and Power Efficient Intelligence with Neuromorphic Learning Machines

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