HfO/sub 2/ and HfAlO for CMOS: thermal stability and current transport

Zhu, Wenjuan; Ma, T.P.; Tamagawa, T.; Di, Yunxiang; Kim, J.; Carruthers, R.; Gibson, M.; Furukawa, Toshio

doi:10.1109/iedm.2001.979541

Cited by 72 publications

(66 citation statements)

References 6 publications

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“…Techniques being explored include atomic layer deposition ͑ALD͒, 11 ion beam assisted deposition 12 and jet vapor deposition. 13 The structure of as-deposited HfO 2 films is not yet fully resolved. For instance, various experimental studies found that HfO 2 films deposited by ALD at 300°C using HfCl 4 and H 2 O as precursors are polycrystalline, and mainly consist of the monoclinic phase with the ͑111͒ surface exhibited as the main growth face.…”

Section: Introductionmentioning

confidence: 99%

First-principles calculations of structural and electronic properties of monoclinic hafnia surfaces

2006

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We have carried out a systematic theoretical study of the surfaces of monoclinic hafnia ͑HfO 2 ͒ using plane waves and density functional theory based on the generalized gradient approximation. The fully relaxed structures of the bulk phases of HfO 2 are found to be in excellent agreement with experimental data, the monoclinic phase being the most stable. Simulations of the monoclinic phase surfaces indicate a large relaxation which reduces the total surface energy of all nine faces considered by between 23% and 36%, with a strong correlation between the unrelaxed and relaxed surface energies. Our calculations predict that the ͑111͒ and ͑111͒ faces of the monoclinic phase have the lowest surface energies and are hence the most stable faces. An analysis of the total and partial electronic density of states of bulk monoclinic HfO 2 reveals that the outer valence band significantly mixes the O 2p and Hf 5d atomic states indicating some covalency of the Hf-O bonds. The total density and partial density of states of the monoclinic surfaces exhibit a surface state corresponding to the surface O 2s states in the inner valence band region.

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Section: Introductionmentioning

confidence: 99%

First-principles calculations of structural and electronic properties of monoclinic hafnia surfaces

2006

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“…12 The as-deposited structure of HfO 2 films is also at issue. Zhu et al 12 report that as-deposited JVD HfO 2 does not show a clear crystalline peak in x-ray diffraction, indicating that the film is amorphous. Amorphous layers are generally preferred for gate oxides, but a polycrystalline layer may also be acceptable.…”

Section: Introductionmentioning

confidence: 99%

“…The thermal stability of HfO 2 films in contact with Si and SiO 2 has been studied for HfO 2 deposited by atomic layer deposition ͑ALD͒, 16 ion beam assisted deposition, 17 metalorganic chemical vapor deposition, 18 and jet vapor deposition ͑JVD͒. 12 The as-deposited structure of HfO 2 films is also at issue. Zhu et al 12 report that as-deposited JVD HfO 2 does not show a clear crystalline peak in x-ray diffraction, indicating that the film is amorphous.…”

Section: Introductionmentioning

confidence: 99%

“…HfO 2 is compatible with polysilicon processing, [2][3][4][5][6] has a high dielectric constant of ϳ16 -25, 2,7-9 and has demonstrated very encouraging initial device characteristics. [10][11][12][13][14][15] The thermal stability of high-materials in direct contact with Si and SiO 2 has also emerged as a key issue in selecting suitable high-candidates. The thermal stability of HfO 2 films in contact with Si and SiO 2 has been studied for HfO 2 deposited by atomic layer deposition ͑ALD͒, 16 ion beam assisted deposition, 17 metalorganic chemical vapor deposition, 18 and jet vapor deposition ͑JVD͒.…”

Section: Introductionmentioning

confidence: 99%

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Morphology and crystallization kinetics in HfO2 thin films grown by atomic layer deposition

Gong

Wilk³

et al. 2003

Journal of Applied Physics

165

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We report the effects of annealing on the morphology and crystallization kinetics for the high-gate dielectric replacement candidate hafnium oxide (HfO 2 ). HfO 2 films were grown by atomic layer deposition ͑ALD͒ on thermal and chemical SiO 2 underlayers. High-sensitivity x-ray diffractometry shows that the as-deposited ALD HfO 2 films on thermal oxide are polycrystalline, containing both monoclinic and either tetragonal or orthorhombic phases with an average grain size of ϳ8.0 nm. Transmission electron microscopy shows a columnar grain structure. The monoclinic phase predominates as the annealing temperature and time increase, with the grain size reaching ϳ11.0 nm after annealing at 900°C for 24 h. The crystallized fraction of the film has a strong dependence on annealing temperature but not annealing time, indicating thermally activated grain growth. As-deposited ALD HfO 2 films on chemical oxide underlayers are amorphous, but show strong signatures of ordering at a subnanometer level in Z-contrast scanning transmission electron microscopy and fluctuation electron microscopy. These films show the same crystallization kinetics as the films on thermal oxide upon annealing.

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“…There is a concern that the mobility of the channel carriers may be degraded by interactions with these soft phonons. [8][9][10][11][12][13][14][15][16][17][18] These metal oxides have reasonably high dielectric constants and band gaps (see Figure 3). Both ZrO 2 and HfO 2 devices have demonstrated a many orders of magnitude reduction in gate leakage with an EOT around 1.0 nm and well-behaved t r a n s i s t o r s .…”

Section: Oxygen Diffusion Through the Grain Boundary Of Metal Oxidementioning

confidence: 99%

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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HfO/sub 2/ and HfAlO for CMOS: thermal stability and current transport

Cited by 72 publications

References 6 publications

First-principles calculations of structural and electronic properties of monoclinic hafnia surfaces

First-principles calculations of structural and electronic properties of monoclinic hafnia surfaces

Morphology and crystallization kinetics in HfO2 thin films grown by atomic layer deposition

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

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