Hf
                  O
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           and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition

Frank, Martin M.; Wilk, G. D.; Starodub, D.; Gustafsson, T.; Garfunkel, Eric; Chabal, Yves J.; Grazul, John; Muller, David A.

doi:10.1063/1.1899745

Cited by 334 publications

(222 citation statements)

References 26 publications

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“…1͑a͔͒, as seen by previous groups. 17,18 There is also detectable Ga-O bond formation for the atomic hydrogen-treated sample after Al 2 O 3 deposition, in contrast to the H-cleaned surface prior to Al 2 O 3 deposition. As a result, As-O and Ga-O species are similar in concentration for these two post-ALD surfaces ͑not shown͒.…”

mentioning

confidence: 99%

Frequency dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation

Hinkle

Sonnet

Vogel

et al. 2007

Applied Physics Letters

101

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The method of surface preparation on n-type GaAs, even with the presence of an amorphous-Si interfacial passivation layer, is shown to be a critical step in the removal of accumulation capacitance frequency dispersion. In situ deposition and analysis techniques were used to study different surface preparations, including NH 4 OH, Si-flux, and atomic hydrogen exposures, as well as Si passivation depositions prior to in situ atomic layer deposition of Al 2 O 3 . As-O bonding was removed and a bond conversion process with Si deposition is observed. The accumulation capacitance frequency dispersion was removed only when a Si interlayer and a specific surface clean were combined. © 2007 American Institute of Physics. ͓DOI: 10.1063/1.2801512͔GaAs has once again attracted attention as an alternative substrate for metal oxide semiconductor ͑MOS͒ technologies. The advantages of GaAs over silicon are well-known, mainly having a higher electron mobility and breakdown voltage as well as a direct band gap suggesting GaAs for a wide range of devices. The elimination of anomalous frequency dispersion of the accumulation capacitance of GaAs MOS devices is a major motivation behind surface and interface treatment studies. Previous reports have attributed this dispersion, viz., the reduction of maximum capacitance with increasing measurement frequency, to a high density of interface states which results in Fermi-level pinning. Recent studies have indicated that the disruption of As-O bonding at the dielectric/GaAs interface results in an unpinned interface. 1 Revisiting earlier works on Si passivation of GaAs surfaces ͑see, for example, Refs. 2 and 3͒, recent reports of Si deposition on GaAs for surface passivation in conjunction with high-k dielectrics ͑for example, Refs. 4 and 5͒, have stimulated this study using in situ deposition and analysis methods. In this letter, in situ analysis techniques are used to correlate differences in electrical characteristics caused by different surface treatments employed on the technologically relevant n-type GaAs surface for use in enhancement mode transistors.The samples used in this work were n-type Si-doped GaAs wafers with a doping concentration of 5 ϫ 10 17 cm −3 . One set of samples was degreased in acetone, methanol, and isopropyl alcohol for 1 min each, followed by a 3 min etch in 29% NH 4 OH, 6 and dried with N 2 , while another set was prepared, in situ with no chemical treatment, using a hydrogen cracker source ͑cell temperature of 1400°C, P H 2 =1 ϫ 10 −6 mbar͒ producing atomic H with a substrate temperature of 430°C for 30 min. 7,8 Silicon of various thicknesses was deposited at room temperature on treated GaAs by e-beam evaporation ͑deposition rate= 18-132 Å / min in a multitechnique deposition/characterization system ͑base pressure= 2 ϫ 10 −11 mbar͒. 9 MOS capacitors were made using such treated surfaces followed by atomic layer deposition ͑ALD͒ of 10 nm of Al 2 O 3 using trimethylaluminum ͑TMA͒ and H 2 O at 300°C in an adjacent chamber and ex situ, rf sputtered TaN as the gat...

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mentioning

confidence: 99%

Frequency dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation

Hinkle

Sonnet

Vogel

et al. 2007

Applied Physics Letters

101

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“…3 Very thin homogeneous high-k oxide layers can routinely be formed by atomic layer deposition (ALD), 2, 4, 5 where even a self-cleaning effect on the native oxide has been observed. [6][7][8][9] Nevertheless, the stoichiometry of the interface between the III-V semiconductor and the high-k dielectric is still not fully controlled and plays a crucial role for the device performance.…”

Section: Author(s) All Article Content Except Where Otherwise Notedmentioning

confidence: 99%

Interface characterization of metal-HfO2-InAs gate stacks using hard x-ray photoemission spectroscopy

et al. 2013

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MOS devices based on III-V semiconductors and thin high-k dielectric layers offer possibilities for improved transport properties. Here, we have studied the interface structure and chemical composition of realistic MOS gate stacks, consisting of a W or Pd metal film and a 6- or 12-nm-thick HfO2 layer deposited on InAs, with Hard X-ray Photoemission Spectroscopy. In and As signals from InAs buried more than 18 nm below the surface are clearly detected. The HfO2 layers are found to be homogeneous, and no influence of the top metal on the sharp InAs-HfO2 interface is observed. These results bridge the gap between conventional photoemission spectroscopy studies on various metal-free model samples with very thin dielectric layers and realistic MOS gate stacks

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“…To improve the transconductance of a GaAs transistor, high-permittivity (high-k) gate dielectric materials are required for fabrication. Several types of oxide films are being considered for a GaAs MOS transistor, such as Al 2 O 3 formed by atomic layer deposition (ALD) [143], HfO 2 by ALD [144], HfO 2 by plasma oxidation [145], Y 2 O 3 by MBE [146], ZrO 2 by RF sputtering [147] and Y 2 O 3 by RF sputtering [148]. In addition, titanium oxide (TiO x ) MOS diodes were fabricated by sputtering [149], liquid-phase deposition [150] and sol-gel methods [151].…”

Section: Sidewall Gaas Tunnel Junction With Tio X Gate Structurementioning

confidence: 99%

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

Ohno

Oyama

2012

Science and Technology of Advanced Materials

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In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm −2 . They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor.

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Hf O 2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition

Cited by 334 publications

References 26 publications

Frequency dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation

Frequency dispersion reduction and bond conversion on n-type GaAs by in situ surface oxide removal and passivation

Interface characterization of metal-HfO2-InAs gate stacks using hard x-ray photoemission spectroscopy

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

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