Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

Carvalho, Ewerson; Calazans, Ney; Moraes, Fernando

doi:10.1109/rsp.2007.26

Cited by 132 publications

(78 citation statements)

References 2 publications

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“…Smit et al [17] proposed a run-time task assignment algorithm for heterogeneous processors where the task graphs are limited to only a small number of tasks. Carvalho et al proposed [18] a dynamic task mapping scheme which aims to improve the performance by minimizing the channel load. Chou et al [6][7] proposed a number of incremental mapping algorithms.…”

Section: Application Mapping Algorithms For Nocmentioning

confidence: 99%

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Wang

Liu

Yang

et al. 2013

J. Comput. Sci. Technol.

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Abstract3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.

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Section: Application Mapping Algorithms For Nocmentioning

confidence: 99%

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Wang

Liu

Yang

et al. 2013

J. Comput. Sci. Technol.

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“…Carvalho et al [18], proposed a "congestion-aware" mapping heuristic to dynamically map tasks on heterogeneous MpSoCs. This heuristic approach initially assigns master-tasks to selected processors and the slave-tasks are allocated on congestion minimizing manner to reduce the communication traffic.…”

Section: Mpsoc Design Literature Reviewmentioning

confidence: 99%

“…(1) Polis [18] is a framework based on both microcontrollers and ASICs for software and hardware implementation. (2) Metropolis [18] is an extension of Polis that proposed a unified modeling and structure for simulating computation models. (3) Ptolemy [18] is a flexible framework for simulating and prototyping heterogeneous systems.…”

Section: Mpsoc Design Literature Reviewmentioning

confidence: 99%

“…(2) Metropolis [18] is an extension of Polis that proposed a unified modeling and structure for simulating computation models. (3) Ptolemy [18] is a flexible framework for simulating and prototyping heterogeneous systems. (4) Thiele et al [1] proposed a simulation based on distributed operation layer (DOL) which considers concurrency, scalability, mapping optimization, and performance analysis in an effort to yield faster simulation time.…”

Section: Mpsoc Design Literature Reviewmentioning

confidence: 99%

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Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Tafesse

Muthukumar

2013

VLSI Design

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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“…In these real-time systems, task allocation and scheduling problem is a main issue for performance optimization. Several dynamic task allocation methods [9]- [12] and static task allocation methods [13], [14] have been proposed. These allocation methods depend on memory architecture in on-chip networks which can be classified as a single shared memory or multiple private memories.…”

Section: Introductionmentioning

confidence: 99%

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories

Imai

Yoneda

2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a fault diagnosis and reconfiguration method based on the Pair and Swap scheme to improve the reliability and the MTTF (Mean Time To Failure) of network-on-chip based multiple processor systems where each processor core has its private memory. In the proposed scheme, two identical copies of a given task are executed on a pair of processor cores and the results are compared repeatedly in order to detect processor faults. If a fault is detected by mismatches, the fault is identified and isolated using a TMR (Triple Module Redundancy) and the system is reconfigured by the redundant processor cores. We propose that each task is quadruplicated and statically assigned to private memories so that each memory has only two different tasks. We evaluate the reliability of the proposed quadruplicated task allocation scheme in the viewpoint of MTTF. As a result, the MTTF of the proposed scheme is over 4.3 times longer than that of the duplicated task allocation scheme. key words: mean time to failure, network-on-chip, multiple processor system, fault diagnosis, pair and swap

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Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs

Cited by 132 publications

References 2 publications

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories

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