HeteroHalide

School of Mechanical Engineering, Shanghai Jiao Tong University, 200240, Shanghai, China

“…HeteroCL [21] and HeteroFlow [34] extend TVM DSL and optimize code using Halide IR. Halide-HLS [28] and Hetero-Halide [24] work as FPGA back-ends of Halide for efficient image processing. We compare HeteroCL and HeteroHalide Adopting multi-level IRs provides a flexible and systemic way to simplify this implementation process and makes it easier to achieve better performance.…”

“…In contrast, FPGA-friendly optimization strategies tend to pipeline outer loop levels and parallelize inner loop levels through unrolling, arXiv:2401.05154v1 [cs.AR] 10 Jan 2024 and loop fusion mainly reduces resource usage. Frameworks for FPGA accelerators with customized data paths (③): Recent advances in HLS frameworks have explored optimization methods for FPGAs [21], [24], [28], [34], [35]. Halide-HLS [28] and HeteroHalide [24] work as FPGA backends for Halide and generate customized pipelines for image processing.…”

“…Frameworks for FPGA accelerators with customized data paths (③): Recent advances in HLS frameworks have explored optimization methods for FPGAs [21], [24], [28], [34], [35]. Halide-HLS [28] and HeteroHalide [24] work as FPGA backends for Halide and generate customized pipelines for image processing. HeteroCL [21] and HeteroFlow [34] extend TVM DSL and generate spatial architectures on FPGAs.…”

SlidingConv: Domain-Specific Description of Sliding Discrete Cosine Transform Convolution for Halide

“…PolyMage's FPGA expansion [78], HIPACC-FPGA [79], [80] 13 , and HipaccVX [81] 14 have been proposed. Halide has been extended to include an FPGA backend, such as Halide-HLS [82] 15 Halide to FPGAs [83] and Hetero-Halide [84] 16 . Halide has also been extended to other computing units such as DSPs [85], push memory [86] and TensorCore [87].…”

Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns

“…Halide [11] is a C++ DSL for image processing which lets the programmer specify separately what to compute and how to schedule the required data movement. Although the primary target of Halide programs are GPUs and CPUs, recent work has presented HeteroHalide, which targets FPGAs [9]. The programmer can choose from several backends, including SODA [3], which optimizes stencil programs for FPGAs.…”