Heterogeneous multi-core platform for consumer multimedia applications

Kollig,; Osborne,; Henriksson,

doi:10.1109/date.2009.5090857

Cited by 46 publications

(54 citation statements)

References 10 publications

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“…As discussed in [41], the number of latency-critical connections has stayed low and fairly constant during the past six generations of TV Socs in the Nexperia platform. The total bandwidth, however, and the number of latency-tolerant function-specific hardware IPs grows over time.…”

Section: Scalability Analysismentioning

confidence: 99%

“…The deep pipelining makes these Fig. 3 Digital TV SoC block diagram [41] connections latency tolerant. Processor instruction fetches (from cache misses), on the other hand, have very low latency requirements (<100 ns) and have relatively small transaction sizes, but require a limited throughput.…”

Section: Listingmentioning

confidence: 99%

“…3 [41]. As shown in the figure, the SoC contains multiple programmable processors with caches: a MIPS for control, three TriMedia processors for audio/video, one MIPS DSP, and a 8051 processor for power management and control.…”

Section: Listingmentioning

confidence: 99%

“…the latency and throughput requirements of the connections, stem from. Depending on the application, the desired throughput and latency may be analytically computed [35], the outcome of high-level simulation models of the application, or simply guesstimates based on back-of-the-envelope calculations or earlier designs [41]. The design flow makes no distinction of the real-time character, e.g.…”

Section: Design Flowmentioning

confidence: 99%

“…Our two examples are both high-end chips with a high degree of IP integration. The first example resembles a digital TV set-top box ASIC in the line of designs described in [24,41]. The second example is based on an automotive info-tainment ASIC [51,61].…”

Section: Introductionmentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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Section: Scalability Analysismentioning

confidence: 99%

Section: Listingmentioning

confidence: 99%

Section: Listingmentioning

confidence: 99%

Section: Design Flowmentioning

confidence: 99%