Heterogeneous Integration of Compound Semiconductors

Moutanabbir, Oussama; Gösele, U.

doi:10.1146/annurev-matsci-070909-104448

Cited by 139 publications

(100 citation statements)

References 173 publications

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“…Integrating III-V semiconductors and silicon requires overcoming their differences in lattice parameters and thermal expansion coefficient, as well as their polar/non-polar interfaces 2,3 . When constrained to a silicon-bottom cell, the optimum dualjunction solar cell, the simplest multi-junction solar cell, has a theoretical 1-sun peak efficiency between 33 and 43% (refs 4,5) when combined with a 1.7 eV bandgap top cell; this can be achieved with a III-V semiconductor consisting of GaAs 0.8 P 0.2.…”

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confidence: 99%

Surface-passivated GaAsP single-nanowire solar cells exceeding 10% efficiency grown on silicon

Holm¹,

Jørgensen²,

et al. 2013

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Continued development of high-efficiency multi-junction solar cells requires growth of latticemismatched materials. Today, the need for lattice matching both restricts the bandgap combinations available for multi-junctions solar cells and prohibits monolithic integration of high-efficiency III-V materials with low-cost silicon solar cells. The use of III-V nanowires is the only known method for circumventing this lattice-matching constraint, and therefore it is necessary to develop growth of nanowires with bandgaps 41.4 eV. Here we present the first gold-free gallium arsenide phosphide nanowires grown on silicon by means of direct epitaxial growth. We demonstrate that their bandgap can be controlled during growth and fabricate core-shell nanowire solar cells. We further demonstrate that surface passivation is of crucial importance to reach high efficiencies, and present a record efficiency of 10.2% for a core-shell single-nanowire solar cell. I mproving the cost/efficiency ratio of III-V-based multijunction cells can be done through efficiency enhancements, by adding additional junctions to the cell stack 1 or through the lowering of cost by replacing the expensive germanium substrate with silicon. Integrating III-V semiconductors and silicon requires overcoming their differences in lattice parameters and thermal expansion coefficient, as well as their polar/non-polar interfaces 2,3 . When constrained to a silicon-bottom cell, the optimum dualjunction solar cell, the simplest multi-junction solar cell, has a theoretical 1-sun peak efficiency between 33 and 43% (refs 4,5) when combined with a 1.7 eV bandgap top cell; this can be achieved with a III-V semiconductor consisting of GaAs 0.8 P 0.2.The small contact interface between the nanowire and the silicon substrate ensures that strain from lattice mismatch is relaxed within the first few monolayers 6 . Using the method of gallium (Ga)-assisted growth, gold-free perfect single crystal, gallium arsenide (GaAs) nanowires have been grown directly on silicon 7 . Higher bandgap gallium phosphide (GaP) 8 and gallium arsenide phosphide (GaAsP) 9,10 nanowires have also been grown, but only using gold as growth catalyst. Gold is incompatible with silicon 11 , and has been shown to incorporate into the III-V crystal 12 and degrade the optoelectronic properties of the nanowires 13 . In addition, a sparse array of nanowires can absorb almost all incoming light 14 , meaning that only minute amounts of the expensive III-V material is needed for making a nanowire top cell. Devices consisting of a contacted ensemble of free-standing nanowires have been exposed to temperature changes of up to 200 K, demonstrating that their strain-relieving ability is able to overcome the difference in thermal expansion 15 . To fully utilize their advantage with regards to non-lattice-matched growth, the nanowires themselves must also be able to function well as solar cells. ResultsGa-assisted GaAs 0.8 P 0.2 nanowire growth. High-quality GaAsP nanowires were grown without the use of a buffer la...

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Surface-passivated GaAsP single-nanowire solar cells exceeding 10% efficiency grown on silicon

Holm¹,

Jørgensen²,

et al. 2013

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“…3 This has sparked interest in developing processes for strain control in Si devices and nanostructures. With recent progress in direct wafer bonding and thin layer transfer techniques, 4,5 tensile strained Si can be grown on a relaxed SiGe and transferred onto a SiO 2 -capped Si wafer achieving the strained Si-on-insulator (SSOI) substrate. SSOI combines the advantages of Si-on-insulator technology 6 with that of strained Si.…”

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Elastic relaxation in an ultrathin strained silicon-on-insulator structure

Xiong

Moutanabbir

Huang

et al. 2011

Applied Physics Letters

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Coherent x-ray diffraction was used to study the relaxation in single ultrathin strained silicon structures with nanoscale accuracy. The investigated structure was patterned from 20 nm thick strained silicon-on-insulator substrate with an initial biaxial tensile strain of 0.6%. Two-dimensional maps of the post-patterning relaxation were obtained for single 1 × 1 μm2 structures. We found that the relaxation is localized near the edges, which undergo a significant contraction due to the formation of free surfaces. The relaxation extent decreases exponentially towards the center with a decay length of 50 nm. Three-dimensional simulations confirmed that over-etching is needed to explain the relaxation behavior.

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“…In order to accomplish this, relatively high implantation fluences of hydrogen ion implantation into subsurface layers are utilized for ion cut technology in the order of E 17 cm −2 . The hydrogen implantation process into the AlN is accompanied by numerous physical processes that lead to a wide range of damage related structures, including H-defect complexes, point defect clusters, and free H. 22,23 In the TEM cross-sectional micrograph of Figure 1a a H ion implantation at 50 keV that caused a broad damage band is shown. The damaged band slightly spread over a 200-nm-thick layer occurring at approximately 400-500 nm below the AlN sample surface.…”

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confidence: 99%

Effect of Hydrogen Implantation on the Mechanical Properties of AlN throughout Ion-Induced Splitting

Mamun

Tapily

Moutanabbir

et al. 2018

ECS J. Solid State Sci. Technol.

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The ability to transfer bulk quality III-N thin layers onto foreign platforms is a powerful strategy to enable high-efficiency and low-cost optoelectronic devices. Ion-cut using sub-surface defect engineering has been an effective process to split and transfer a variety of semiconductors. With this perspective, hydrogen-implanted AlN samples were annealed in air at temperatures ranging from 300 • C to 600 • C for 5 min to study the influence of pre-layer splitting treatments on the nanomechanical properties. There is a clear dependence of the hardness on implanted hydrogen implantation fluence. We observe that the as-implanted hardness increased from 18 GPa for the virgin reference sample to ∼25 GPa for the highest fluence of 3 × 10 17 H cm −2 prior to annealing. In the case of reference single crystalline Si samples, a significant drop in the hardness and elastic modulus is observed in the H implantation-induced damage zone subsequent to thermal annealing , while for crystalline epitaxial AlN samples with 0.5 × 10 17 and 2.0 × 10 17 H implant fluences, the hardness increases and peaks until the thermal annealing temperature reaches 350 • C and subsequently begins to drop thereafter for higher annealing temperatures. However, for the 1.0 × 10 17 H implantation fluence the hardness continues to increase with increasing thermal annealing temperature. The remarkable growth in the optoelectronic industry is attributed to group III-nitride compound semiconductors such as GaN, AlN, and InN. [1][2][3][4][5][6] Due to the wide bandgap nature and the piezoelectric properties of AlN and GaN 7,8 and the high electron mobility and small bandgap of InN, 9 significant interest in the fabrication of these materials is palpable.The exploitation of the full potential of the group III-nitride compound semiconductors in the emerging optoelectronic technologies such as deep ultraviolet DUV light emitting diodes LEDs, surface acoustic wave sensors (SAWs), RF filters in MEMS technologies etc., faces major challenges namely the lack of or the high cost of high crystalline quality material. Although bulk group III-nitride wafers are excessively expensive, only 2-4 inch bulk GaN wafers are commercially available. In general, due to its high thermal stability, single crystal sapphire substrates are used for the epitaxial growth of group III-nitride layers. Due to lattice and thermal mismatch between the III-N semiconductor materials and growth on substrates such as sapphire, it is documented that the grown layers tend to be defective with misfit dislocations. Reducing interfacial defect density requires the growth of very thick layers which is a very lengthy process. Bulk wafers are obtained from these thick layers. In order to reduce the cost of these bulk materials one approach would be to implement the ion-cut process. [10][11][12] The ion-cut process, which is based on ion (H and/or He) implantation and wafer bonding, is used to transfer crystalline layers onto substrates that produce heterostructures that cannot be produced by other...

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Heterogeneous Integration of Compound Semiconductors

Cited by 139 publications

References 173 publications

Surface-passivated GaAsP single-nanowire solar cells exceeding 10% efficiency grown on silicon

Surface-passivated GaAsP single-nanowire solar cells exceeding 10% efficiency grown on silicon

Elastic relaxation in an ultrathin strained silicon-on-insulator structure

Effect of Hydrogen Implantation on the Mechanical Properties of AlN throughout Ion-Induced Splitting

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