Heterogeneous B^∗-trees for analog placement with symmetry and regularity considerations

Abstract

Symmetry constraints and regular structures are two major considerations for expert analog layout designers. Symmetry constraints are specified to place matched modules symmetrically with respect to some common axes to reduce unwanted electrical effects. Regular structures are commonly followed by experienced designers to enhance routability and suppress parasitics induced by extra bends of wires and via cost. In this paper, we propose a heterogeneous B*-tree representation to consider symmetry and regularity simultaneously. Corresponding moves and a new regularity cost modelling for the representation are also presented. Experimental results show that our approach can efficiently generate regularly structured placement satisfying all symmetry constraints. For example, our placer achieves a 18X runtime speedup, 28% smaller area, and 68% shorter wirelength than the previous work, based on placement results, and 60% fewer overflows, 39% fewer vias, and 86% shorter routed wirelength, based on global routing results.

Laser

“…Previous works did not consider the required routing resource in the placement stage [8][9][10] or used an unfaithful congestion to adjust the generated placement [12][13][14]. To accurately predict the required routing resource during placement and generate nonstochastic placements, a routability-aware analog placement flow is proposed.…”

“…In the literature, layout automation techniques for analog circuits are also a popular research direction [8][9][10][11][12][13][14]. In recent years, many researches [8][9][10] focus on studying the analog placement problem to consider the extra layout constraints such as matching, proximity, etc. The succeeding routing issue is often not considered due to the small number of nets in analog circuits.…”

“…In order to reduce the parasitic capacitance and crosstalk effect, the routing nets above the active area of the devices are often avoided in the routing step [11]. Previous works [8][9][10] do not consider the routing resource in the placement stage and will incur compact placements which are not practical in analog designs. Previous works [12][13][14] perform congestion-driven adjustments during placement.…”

Simultaneous analog placement and routing with current flow and current density considerations

“…However, most of the traditional analog layout synthesis algorithms address on either placement or routing individually [3,5,6,11,13,14,16,17,18,19,21,23,24]. As a result, placement is performed followed by routing, leading to an ordered synthesis flow.…”

Slicing Floorplans with Handling Symmetry and General Placement Constraints

“…Young et al [3] presented an approach to successfully solve the mixed constraint-driven placement problem with symmetry, common centroid and general constraints based on sequence pair (SP) [2]. In order to alleviate the congestion and improve the routability, some works [4], [6] introduced the regular structure to the non-slicing floorplan based on sequence pair and B*-trees [7] respectively. Basically, these regular structures allow us to assign proportional channels in the placement for routing job.…”