Hermes: A fast cross-ISA binary translator with post-optimization

Zhang, Xiaochun; Guo, Qi; Chen, Tianshi; Hu, Weiwu

doi:10.1109/cgo.2015.7054204

Cited by 12 publications

(3 citation statements)

References 20 publications

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“…In addition, there are several schemes proposed to optimize DBT systems [43,58,[65][66][67]77]. Basically, our HTM virtualization mechanism can cooperate with these optimizations to further improve the emulation performance.…”

Section: Related Workmentioning

confidence: 99%

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Wang

Yew

Zhai

et al. 2020

Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization

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System virtualization is a key enabling technology. However, existing virtualization techniques suffer from a significant limitation due to their limited cross-ISA support for emerging architecture-specific hardware extensions. To address this issue, we make the first attempt at hardware transactional memory (HTM), which has been supported by modern multi-core processors and used by more and more applications to simplify concurrent programming. In particular, we propose an efficient and scalable mechanism to support cross-ISA virtualization of HTMs. The mechanism emulates guest HTMs using host HTMs, and tries to preserve as much as possible the performance and the scalability of guest applications. Experimental results on STAMP benchmarks show that an average of 2.3X and 12.6X performance speedup can be achieved respectively for x86_64 and PowerPC64 guest applications on an x86_64 host machine. Moreover, it can attain similar scalability to the native execution of the applications. CCS Concepts• Software and its engineering → Justin-time compilers; Runtime environments; Dynamic compilers; Virtual machines; Multithreading; • Hardware → Emerging languages and compilers.

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Section: Related Workmentioning

confidence: 99%

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Wang

Yew

Zhai

et al. 2020

Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization

View full text Add to dashboard Cite

show abstract

“…There are also several schemes to optimize DBT systems in previous research work [16,22,35,37,39]. In general, our approach can leverage those optimizations to further improve the emulation performance.…”

Section: Delmentioning

confidence: 99%

Improving Dynamically-Generated Code Performance on Dynamic Binary Translators

et al. 2018

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The recent transition in the software industry toward dynamically generated code poses a new challenge to existing dynamic binary translation (DBT) systems. A significant re-translation overhead could be introduced due to the maintenance of the consistency between the dynamicallygenerated guest code and the corresponding translated host code. To address this issue, this paper presents a novel approach to optimize DBT systems for guest applications with dynamically-generated code. The proposed approach can maximize the reuse of previously translated host code to mitigate the re-translation overhead. A prototype based on such an approach has been implemented on an existing DBT system HQEMU. Experimental results on a set of JavaScript applications show that it can achieve a 1.24X performance speedup on average compared to the original HQEMU. CCS Concepts • Software and its engineering → Virtual machines; Just-in-time compilers; Dynamic compilers; Runtime environments; Retargetable compilers; Scripting languages; Software reverse engineering;

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“…Uma ISA define a interface entre a pilha de software e a pilha de hardware, de forma que programas compilados para uma ISA não podem ser executados em outras, se não por meio de emulação [Smith and Nair 2005]. Portanto, com o surgimento de novas ISAs, como o RISC-V, e com a heterogeneidade entre a computação nas nuvens, móvel e da Internet das Coisas, a pesquisa de melhores técnicas de emulação de ISAs para a redução do custo do desenvolvimento e implantação de software tem se tornado cada vez mais importante [Zhang et al 2015]. Principalmente porque, apesar da emulação de programas na mesma ISA terem sobrecarga (empecilho na obtenção de desempenho igual ao nativo) pequena, como demonstrado pelo StarDBT da Intel [Borin and Wu 2009], a emulação de diferentes ISAs ainda possui um tempo de execução maior que duas vezes o da execução nativa mesmo com a aplicação de técnicas sofisticadas como a tradução dinâmica de binários [Zhang et al 2015, Hong et al 2012.…”

Section: Introductionunclassified

Uma Análise da Facilidade de Emulação de Binários RISC-V

Lupori¹,

Rosário²,

Borin³

2018

Anais Da IX Escola Regional De Alto Desempenho De São Paulo (ERAD-SP 2018)

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Cada vez mais a heterogeneidade nos ambientes como a nuvem, dispositivos móveis e Internet das Coisas, tem tornado importante a pesquisa em tradução de binários para ISAs diferentes. Grande parte das sobrecargas computacionais vem da qualidade da tradução e estão ligados com a ISA sendo traduzida. O OpenISA já se demonstrou ser fácil de emular e obteve bons desempenhos de desempenho. Nesse trabalho apresentamos resultados que indicam que o RISC-V também pode ser emulável com baixa sobrecarga de desempenho, menos de 30%.

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Hermes: A fast cross-ISA binary translator with post-optimization

Cited by 12 publications

References 20 publications

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Improving Dynamically-Generated Code Performance on Dynamic Binary Translators

Uma Análise da Facilidade de Emulação de Binários RISC-V

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