Heracles

Kinsy, Michel A.; Pellauer, Michael; Devadas, Srinivas

doi:10.1145/2435264.2435287

Cited by 33 publications

(3 citation statements)

References 22 publications

(15 reference statements)

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“…From all the flow optimisation works for heterogeneous digital systems design found in literature [15][16][17][18][19][20][21], Highly Agile Masks Made Effortlessly from RTL (HAMMER) [22] is one of the projects closest to our work, as it focuses on workflow automation. It is used within the Chipyard framework [23] to automate its Very Large Scale Integration (VLSI) design flow.…”

Section: Related Workmentioning

confidence: 99%

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case

et al. 2022

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Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital design projects, taking more than 50% of the total project time. Several solutions have been developed with the goal of automating this task, integrating various steps of the Very Large Scale Integration design flow, but without addressing the exploration of the design space on both the software and hardware sides. Early in the co-design phase, designers break down the system into hardware and software parts taking into account different choices to explore the design space. This work describes the use of a framework for automating the verification of such choices, considering both hardware and software development flows. The framework automates compilation of software, cycle-true simulations and analyses on synthesised netlists. It accelerates the design space exploration exploiting the GNU Make tool, and we focus on ensuring consistency of results and providing a mechanism to obtain reproducibility of the design flow. In design teams, the last feature increases cooperation and knowledge sharing from single expert to the whole team. Using flow recipes, designers can configure various third-party tools integrated into the modular structure of the framework, and make workflow execution customisable. We demonstrate how the developed framework can be used to speed up the setup of the evaluation flow of an Elliptic-Curve-Cryptography accelerator, performing post-synthesis analyses. The framework can be easily configured taking approximately 30 min, instead of few days, to build up an environment to assess the accelerator performance and its resistance to simple power analysis side-channel attacks.

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Section: Related Workmentioning

confidence: 99%

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case

et al. 2022

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“…From the result of hardware utilization, we found that the size of the hardware generated from the converted Verilog HDL code by the translation tool is practicable. For example, Heracles [11], that is an RTL based many-core simulation environment, implements a similar many-core processor to our processor. Its node mainly consists of a 7stage pipelined 32-bit MIPS processor core, instruction/data caches, and virtual channel NoC router.…”

Section: Evaluation Of Simulation Speedmentioning

confidence: 99%

“…Its node mainly consists of a 7stage pipelined 32-bit MIPS processor core, instruction/data caches, and virtual channel NoC router. In [11], in spite of using of hand-written Verilog HDL design methodology and a Virtex-6 LX550T FPGA which has 10% more slices than our targeted FPGA, the authors could implement an at most 25-node many-core processor because of its core complexity, whose node has a 32 KB local memory. Compared with that, our processor core is simpler but ArchHDL are able to generate a many-core processor with about twice core counts instead.…”

Section: Evaluation Of Simulation Speedmentioning

confidence: 99%

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment

Sato

Kobayashi

Kise

2018

IEICE Trans. Inf. & Syst.

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LSIs are generally designed through four stages including architectural design, logic design, circuit design, and physical design. In architectural design and logic design, designers describe their target hardware in RTL. However, they generally use different languages for each phase. Typically a general purpose programming language such as C or C++ and a hardware description language such as Verilog HDL or VHDL are used for architectural design and logic design, respectively. That is time-consuming way for designing a hardware and more efficient design environment is required. In this paper, we propose a new hardware modeling and high-speed simulation environment for architectural design and logic design. Our environment realizes writing and verifying hardware by one language. The environment consists of (1) a new hardware description language called ArchHDL, which enables to simulate hardware faster than Verilog HDL simulation, and (2) a source code translation tool from ArchHDL code to Verilog HDL code. ArchHDL is a new language for hardware RTL modeling based on C++. The key features of this language are that (1) designers describe a combinational circuit as a function and (2) the ArchHDL library realizes non-blocking assignment in C++. Using these features, designers are able to write a hardware transparently from abstracted level description to RTL description in Verilog HDL-like style. Source codes in ArchHDL is converted to Verilog HDL codes by the translation tool and they are used to synthesize for FPGAs or ASICs. As the evaluation of our environment, we implemented a practical many-core processor in ArchHDL and measured the simulation speed on an Intel CPU and an Intel Xeon Phi processor. The simulation speed for the Intel CPU by ArchHDL achieves about 4.5 times faster than the simulation speed by Synopsys VCS. We also confirmed that the RTL simulation by ArchHDL is efficiently parallelized on the Intel Xeon Phi processor. We convert the ArchHDL code to a Verilog HDL code and estimated the hardware utilization on an FPGA. To implement a 48-node many-core processor, 71% of entire resources of a Virtex-7 FPGA are consumed.

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