Helper threads via virtual multithreading

Wang, P.H.; Collins, Jamison D.; Kim, Dong-Keun; Greene, Bill; Chan, Kai-Ming; Yunus, Aamir B.; Sych, Terry; Moore, Stephen F.; Shen, John Paul; Wang, Hong

doi:10.1109/mm.2004.75

Cited by 15 publications

(8 citation statements)

References 10 publications

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“…Many works have improved single-thread performance by using helper threads [Luk 2001;Roth and Sohi 2001;Tiwari et al 2010;Wang et al 2004;Xekalakis et al 2009]. In Luk [2001] and Roth and Sohi [2001], to tolerate memory bottlenecks, the helper threads perform pre-execution with idle hardware resources.…”

Section: Comparison To Hardware Accelerated Queuesmentioning

confidence: 99%

Automatic parallelization of fine-grained metafunctions on a chip multiprocessor

Lee

Tuck

2013

ACM Trans. Archit. Code Optim.

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Due to the importance of reliability and security, prior studies have proposed inlining metafunctions into applications for detecting bugs and security vulnerabilities. However, because these software techniques add frequent, fine-grained instrumentation to programs, they often incur large runtime overheads. In this work, we consider an automatic thread extraction technique for removing these fine-grained checks from a main application and scheduling them on helper threads. In this way, we can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes. Our parallelization strategy extracts metafunctions from a single threaded application and executes them in customized helper threads-threads constructed to mirror relevant fragments of the main program's behavior in order to keep communication and overhead low. To get good performance, we consider optimizations that reduce communication and balance work among many threads. We evaluate our parallelization strategy on Mudflap, a pointer-use checking tool in GCC. To show the benefits of our technique, we compare it to a manually parallelized version of Mudflap. We run our experiments on an architectural simulator with support for fast queueing operations. On a subset of SPECint 2000, our automatically parallelized code using static load balance is only 19% slower, on average, than the manually parallelized version on a simulated eight-core system. In addition, our automatically parallelized code using dynamic load balance is competitive, on average, to the manually parallelized version on a simulated eightcore system. Furthermore, all the applications except parser achieve better speedups with our automatic algorithms than with the manual approach. Also, our approach introduces very little overhead in the main program-it is kept under 100%, which is more than a 5.3× reduction compared to serial Mudflap.

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Section: Comparison To Hardware Accelerated Queuesmentioning

confidence: 99%

Automatic parallelization of fine-grained metafunctions on a chip multiprocessor

Lee

Tuck

2013

ACM Trans. Archit. Code Optim.

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“…Many works have improved singlethread performance by using helper threads [16,28,35,37,38]. In [16,28], to tolerate memory bottlenecks, the helper threads perform pre-execution with idle hardware resources.…”

Section: Related Workmentioning

confidence: 99%

Automatic parallelization of fine-grained meta-functions on a chip multiprocessor

Lee

Tuck

2011

International Symposium on Code Generation and Optimization (CGO 2011)

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Due to the importance of reliability and security, prior studies have proposed inlining meta-functions into applications for detecting bugs and security vulnerabilities. However, because these software techniques add frequent, finegrained instrumentation to programs, they often incur large runtime overheads. In this work, we consider an automatic thread extraction technique for removing these fine-grained checks from a main application and scheduling them on helper threads. In this way, we can leverage the resources available on a CMP to reduce the latency and overhead of fine-grained checking codes.Our parallelization strategy automatically extracts metafunctions from the main application and executes them in customized helper threads -threads constructed to mirror relevant fragments of the main program's behavior in order to keep communication and overhead low. To get good performance, we consider optimizations that reduce communication and balance work among many threads.We evaluate our parallelization strategy on Mudflap, a pointer-use checking tool in GCC. To show the benefits of our technique, we compare it to a manually parallelized version of Mudflap. We run our experiments on an architectural simulator with support for fast queueing operations. On a subset of SPECint 2000, our automatically parallelized code is only 29% slower, on average, than the manually parallelized version on a simulated 8-core system. Furthermore, two applications achieve better speedups using our algorithms than with the manual approach. Also, our approach introduces very little overhead in the main program -it is kept under 100%, which is more than a 5.3× reduction compared to serial Mudflap.

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“…There is a lot of experience in using and programming multiprocessors, multicores, multithreaded, and vector systems in the highperformance domain. For example, helper threads [Wang et al 2004] have been proposed as a means to achieve better performance in the context of multithreaded execution. Applying the knowledge gained there is a good starting point for embedded applications.…”

Section: Parallel Programming Modelsmentioning

confidence: 99%

On the exploitation of loop-level parallelism in embedded applications

Kejariwal

Veidenbaum

Nicolau

et al. 2009

ACM Trans. Embed. Comput. Syst.

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Advances in the silicon technology have enabled increasing support for hardware parallelism in embedded processors. Vector units, multiple processors/cores, multithreading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. To what extent the available hardware parallelism can be exploited is directly dependent on the amount of parallelism inherent in the given application and the congruence between the granularity of hardware and application parallelism. This paper discusses how loop-level parallelism in embedded applications can be exploited in hardware and software. Specifically, it evaluates the efficacy of automatic loop parallelization and the performance potential of different types of parallelism, viz., true thread-level parallelism (TLP), speculative thread-level parallelism and vector parallelism, when executing loops. Additionally, it discusses the interaction between parallelization and vectorization. Applications from both the industry-standard EEMBC R 1 1.1, EEMBC 2.0 and the academic MiBench embedded benchmark suites are analyzed using the Intel R 2 C compiler. The results show the performance that can be achieved today on real hardware and using a production compiler, provide upper bounds on the performance potential of the different types of thread-level parallelism, and point out a number of issues that need to be addressed to improve performance. The latter include parallelization of libraries such as libc and design of parallel algorithms to allow maximal exploitation of parallelism. The results also point to the need for developing new benchmark suites more suitable to parallel compilation and execution.

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Helper threads via virtual multithreading

Cited by 15 publications

References 10 publications

Automatic parallelization of fine-grained metafunctions on a chip multiprocessor

Automatic parallelization of fine-grained metafunctions on a chip multiprocessor

Automatic parallelization of fine-grained meta-functions on a chip multiprocessor

On the exploitation of loop-level parallelism in embedded applications

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