Heavy Ions Induced Single Event Upsets Testing of the 28 nm Xilinx Zynq-7000 All Programmable SoC

Tambara, Lucas Antunes; Kastensmidt, Fernanda Lima; Medina, N. H.; Added, N.; Aguiar, Vitor A. P.; Aguirre, Fernando; Macchione, Eduardo Luiz Augusto; Silveira, M. A. G.

doi:10.1109/redw.2015.7336716

Cited by 35 publications

(10 citation statements)

References 4 publications

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“…Let the module SEU rate λs = 0.012/h based on the data in [24,25]. According to the data in [18], λ s is approximately twice λ d (DEU rate). Remember that in [7], the ratio used was λ s = 10 λ d ; this ratio was based on the data in [3,15].…”

Section: Reliability Resultsmentioning

confidence: 99%

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FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

et al. 2020

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Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

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Section: Reliability Resultsmentioning

confidence: 99%

“…In this subsection, the reliability was studied for the 5MR and 6MR fault tolerance techniques using different ratios between λs and λ d as the ratio may be 10 or less [17,18]. Figures 2 and 3 show Markov models for 5MR and 6MR [10,19].…”

Section: Effect Of Failure Rates Ratio On Reliabilitymentioning

confidence: 99%

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

et al. 2020

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“…While more sensitive to transient faults than ASICs [7], [8], FPGAbased Soft-SoCs have been shown to offer excellent FDIR potential for miniaturized satellites [9]. Transients in critical parts of the FPGA fabric can be scrubbed [10], while permanent faults may be compensated through reconfiguration with differently routed configuration variants [11].…”

Section: Background and Related Workmentioning

confidence: 99%

Fault-Tolerant Nanosatellite Computing on a Budget

Fuchs¹,

Murillo²,

Plaat³

et al. 2019

Preprint

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We present an on-board computer architecture designed for small satellites (<50kg), which exploits software-fault-tolerance to achieve strong fault coverage with commodity hardware. Micro-and nanosatellites have become popular platforms for a variety of commercial and scientific applications, but today are considered suitable mainly for short and low-priority space missions due to their low reliability. In part, this can be attributed to their reliance upon cheap, low-feature size, COTS components originally designed for embedded and mobilemarket applications, for which traditional hardware-voting concepts are ineffective. Software-fault-tolerance has been shown to be effective for such systems, but have largely been ignored by the space industry due to low maturity, as most have only been researched in theory. In practice, designers of payload instruments and miniaturized satellites are usually forced to sacrifice reliability in favor of delivering the level of performance necessary for cutting-edge science and innovative commercial applications. Thus, we developed a set of software measures facilitating fault tolerance based upon thread-level coarse-grain lockstep, which we validated through fault-injection. To offer strong long-term fault coverage, our architecture is implemented as tiled MPSoC on an FPGA, utilizing partial reconfiguration, as well as mixed criticality. This architecture can satisfy the high performance requirements of current and future scientific and commercial space missions at very low cost, while offering the strong fault-coverage guarantees necessary for platform control even for missions with a long duration. This architecture was developed for a 4-year ESA project. Together with two industrial partners, we are developing a prototype to then undergo radiation testing.

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“…Other works have explored architectural components. In [14] and [15] cache memories are studied to determine their resilience to radiation environments. In [16] operating systems are studied to characterize their behavior under radiation.…”

Section: Related Workmentioning

confidence: 99%

Evaluation of the Suitability of NEON SIMD Microprocessor Extensions Under Proton Irradiation

Lindoso

García-Valderas

Entrena

et al. 2018

IEEE Trans. Nucl. Sci.

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This work analyzes the suitability of SIMD (Single Instruction Multiple Data) extensions of current microprocessors under radiation environments. SIMD extensions are intended for software acceleration, focusing mostly in applications that require high computational effort, which are common in many fields such as computer vision. SIMD extensions use a dedicated coprocessor that makes possible packing several instructions in one single extended instruction. Applications that require high performance could benefit from the use of SIMD coprocessors, but their reliability needs to be studied. In this work NEON™, the SIMD coprocessor of ARM microprocessors, has been selected as a case study to explore the behavior of SIMD extensions under radiation. Radiation experiments of ARM CORTEX™-A9 microprocessor have been accomplished with the objective of determining how the use of this kind of coprocessors can affect the system reliability.

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Heavy Ions Induced Single Event Upsets Testing of the 28 nm Xilinx Zynq-7000 All Programmable SoC

Cited by 35 publications

References 4 publications

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

Fault-Tolerant Nanosatellite Computing on a Budget

Evaluation of the Suitability of NEON SIMD Microprocessor Extensions Under Proton Irradiation

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