Heavy ion SEE test of 2 Gbit DDR3 SDRAM

Herrmann, Martin; Grurmann, Kai; Gliem, F.; Kettunen, H.; Ferlet-Cavrois, V.

doi:10.1109/radecs.2011.6131333

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Ill From Evaluation Board To Tester1

Clear Content In the Memory1

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Cited by 10 publications

(2 citation statements)

References 7 publications

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“…This would be a serious drawback for potentially SEL susceptible parts. However, recent test results [5,6,7] have not shown SEL susceptibility in DDR2 and DDR3 SDRAMS. Moreover, while the need to cycle power to a SDRAM that has suffered a SEFI requires cycling power to the entire evaluation board and then reloading the test program, this can be accomplished in a matter of minutes.…”

Section: Ill From Evaluation Board To Testermentioning

confidence: 93%

Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

Ladbury

Berg

Wilcox

et al. 2013

IEEE Trans. Nucl. Sci.

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Section: Ill From Evaluation Board To Testermentioning

confidence: 93%

Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

Ladbury

Berg

Wilcox

et al. 2013

IEEE Trans. Nucl. Sci.

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“…The clear content in memory resources refers to the situation in which the value read in a memory is 0 due to the particle strike [18]. This effect is principally due to failure happening within the control logic resources.…”

Section: Clear Content In the Memorymentioning

confidence: 99%

Analysis of Single Event Effects on Embedded Processor

et al. 2021

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The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.

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