Heavy Ion Energy Effects in CMOS SRAMs

Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits

“…Upsets in SEU-hardened SRAMs have also been attributed to secondary particles traversing multiple sensitive volumes and causing upsets at lower LETs than are possible from single-node strikes [13]. In [12], we showed data taken at high-and low-energy heavy ion accelerators indicating that in some cases significant differences exist between SEU cross sections as a function of ion energy. While it was conjectured that these differences were due to the effects of nuclear interactions as described in [9], [11], the limited data that were available did not overwhelmingly support this hypothesis.…”

“…4. Note that highand low-energy data on this SRAM were presented in [12], and no significant differences were observed. However, as pointed out in that paper, the measured data covered only three orders of magnitude in SEU cross section and no high-fluence data at low LET had been taken to ensure that a a low-LET "tail" in the upset cross section was not present.…”

“…Downward pointing arrows indicate that the data point is an upper bound and that no upsets (or latchups in the case of SEL data) occurred at this point. Data for Blocks 8-15 were previously analyzed and included in [12], and the characteristics of Block 6 are similar. First, note that the high and low-energy data converge at high LET.…”

“…Like the 256-Kbit bulk SRAM, the SOI SRAM is split into 16 blocks (this time 64 Kbits each) with different-sized feedback resistors. The upper 512 Kbits of the SRAM (blocks [8][9][10][11][12][13][14][15] have the nominal (maximum) size feedback resistors used in the technology, while the other eight 64-Kbit blocks have resistors ranging down to no feedback resistance in Block 0. Fig.…”

Prediction of low-LET ion induced single event upset cross sections for advanced SRAM

“…Therefore, characterization of direct ionization from the low-LET ions is crucial for modern devices. Although heavy ion nuclear interactions have been found crucial in the failure rate of SEU-hardened integrated circuits, which have higher direct ionization threshold LETs [4][5][6][7]; for commercial SRAMs, it has been shown that heavy ion nuclear interactions are not expected to play a significant role, and mission error rates will be dominated by direct ionization events [7,8]. In this paper, we aim at proposing a simple method to estimate upset cross section for six-transistor (6T) bulk complementary metal oxide semiconductor (CMOS) SRAM in a certain tolerance during the design phase.…”