1990
DOI: 10.1016/0022-0248(90)90026-h
|View full text |Cite
|
Sign up to set email alerts
|

Heat treatments of InP wafers

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
4
0

Year Published

1991
1991
2023
2023

Publication Types

Select...
8

Relationship

0
8

Authors

Journals

citations
Cited by 16 publications
(4 citation statements)
references
References 9 publications
0
4
0
Order By: Relevance
“…Hofmann et al 3 have been the first to get real semiinsulating state for InP ͑Ͼ10 7 ⍀ cm͒ by annealing under phosphorus ambiance. This has been reproduced in Japan by Kainosho et al 4 and then has given place to several studies [5][6][7][8][9][10][11] to understand the physical phenomena involved in the compensation mechanism. At present time a general model 11 assumes that an annihilation of intrinsic defects related to donors occurs due to the annealing in phosphorus ambiance.…”
mentioning
confidence: 81%
“…Hofmann et al 3 have been the first to get real semiinsulating state for InP ͑Ͼ10 7 ⍀ cm͒ by annealing under phosphorus ambiance. This has been reproduced in Japan by Kainosho et al 4 and then has given place to several studies [5][6][7][8][9][10][11] to understand the physical phenomena involved in the compensation mechanism. At present time a general model 11 assumes that an annihilation of intrinsic defects related to donors occurs due to the annealing in phosphorus ambiance.…”
mentioning
confidence: 81%
“…One of the possible reasons for the decrease in the surface resistance is the deficiency of P induced in the dry etching [13,23]. While the annealing may recover the crystallinity lost during the dry etching [24], the high temperature treatment can even enhance the composition deficiency.…”
Section: Fabrication Of Narrow Channelsmentioning
confidence: 99%
“…We use a recycling factor corresponding to n-type InP because undoped InP grown using different techniques tends to have n-type background doping of the order of 1x10 15 -1x10 16 cm -3 due to silicon impurity. [22,52,53] III. RESULTS…”
Section: B Device Simulationmentioning
confidence: 99%