Heat Dissipation Capability of Stagger-Stacked Double Data Rate Module

Abstract

In this study, we introduce a stagger-stacked DDR module that comprises one IPD chip (top die) along with four memory chips initially. The steady-state thermal characteristics of this configuration were empirically assessed using a dedicated thermal test vehicle. The purpose of this research is to investigate the module’s junction temperature by adjusting four factors: the thermal conductivity of the molding plastic, chip thickness, chip misalignment length, and the thermal conductivity of the adhesive film. We observed that the junction temperature decreases with an increase in the chip staggered length. An improved orthogonal experimental method was utilized to achieve the optimal design of the module. The optimal junction temperature has decreased by 4.74% compared to the initial value. Additionally, three alternative packaging technologies—cantilever, pyramid, and a combination of cantilever and pyramid—were evaluated for the benchmarking of the thermal performance. Ultimately, the stagger-stacked package demonstrated a reduction in the junction temperature by 3.62%, 7.95%, and 5.63%, respectively, when compared to the three traditional stacked packages.