Heap data management for limited local memory (LLM) multi-core processors

Abstract

This paper presents a scheme to manage heap data in the local memory present in each core of a limited local memory (LLM) multi-core processor. While it is possible to manage heap data semi-automatically using software cache, managing heap data of a core through software cache may require changing the code of the other threads. Cross thread modifications are difficult to code and debug, and only become more difficult as we scale the number of cores. We propose a semi-automatic, and scalable scheme for heap data management that hides this complexity in a library with a much natural programming interface. Furthermore, for embedded applications, where the maximum heap size can be known at compile time, we propose optimizations on the heap management to significantly improve the application performance. Experiments on several benchmarks of MiBench executing on the Sony Playstation 3 show that our scheme is easier to use, and if we know the maximum size of heap data, then our optimizations can improve application performance by an average of 14%.

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

“…Assume that App5 is a critical application with real-time requirements; then mapping the application's data to off-chip memory might not be the best approach as the overhead due to the off-chip accesses might lead it to miss its deadlines. This worsens when designers wish to map their application's instructions to the on-chip SPMs, given that it has been shown that mapping instructions to SPMs may result in greater performance improvements than mapping data alone [4,13,14,33]. As a result, there is a need for dynamic allocation of SPM space considering the priority of the applications in a heterogenous multi-tasking system.…”

“…Our goal is to provide an efficient (dynamic, high performance, low power, secure) resource management layer that supports multi-tasking environments and trusted application execution. In order for programmers to adopt our approach there is a critical need for transparency as there is extensive work addressing both SPM management (static and dynamic) [4,5,10,23,24,31,36,41] as well as scheduling for SPM enabled systems [36,38]. As a result, we intend to provide developers with a set of high-level APIs (Sect.…”

“…Figure 4 shows the high-level diagram of our target platform. Our Chip-Multiprocessor (CMP) resembles the platform used in [6,7,36], which consists of a set of OpenRISC- 4 SPMVisor enhanced chip-multiprocessor like cores, distributed SPMs, an AMBA AHB [2] on-chip bus, enhanced with a secure DMA (S-DMA), and a cryptographic engine (Crypto) similar to the ones in [21,28]. The SPMVisor module behaves as an enhanced arbiter that serves requests from its masters (CPUs) to the on-chip distributed SPMs.…”

“…Traditional SPM allocation schemes have focused primarily on mapping data to SPMs [16,26,31,[36][37][38]41], however, it has been shown that mapping instructions and data (e.g., functions, heap/stack management) onto SPMs yields better performance and energy utilization than mapping data alone [4,24]. As a result, the SPMVisor's APIs allow programmers to prioritize what to bring onto SPM space regardless of whether it is data or instruction blocks.…”

“…Traditional approaches assume that a given application is granted full access to the underlying resources [4,5,10,23,24,31,36,41], however, in multi-tasking environments such approaches will not work as the state of the system (applications running, memory requirements) will vary. Techniques for sharing the on-chip SPMs have been proposed [16,37,38], however, they assume that the applications are known ahead of time.…”