HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

Liu, Zhenyu; Song, Yang; Shao, Ming; Shen, Li; Li, Lingfeng; Ishiwata, Shunichi; Nakagawa, M.; Goto, Satoshi; Ikenaga, Takeshi

doi:10.1109/jssc.2008.2010797

Cited by 79 publications

(46 citation statements)

References 26 publications

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“…Some high-throughput interpolators have been proposed for H.264/AVC in literatures [5][6][7][8][9][10]. Usually, they are embedded in the fractional motion estimation pipeline stage that follows the integer-pel motion estimation.…”

Section: Introductionmentioning

confidence: 99%

An efficient interpolation filter VLSI architecture for HEVC standard

Zhou

Lian

et al. 2015

EURASIP J. Adv. Signal Process.

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The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

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Section: Introductionmentioning

confidence: 99%

An efficient interpolation filter VLSI architecture for HEVC standard

Zhou

Lian

et al. 2015

EURASIP J. Adv. Signal Process.

Self Cite

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“…Except one design [5], architectures for the motion estimation consist of two parts assigned to the integer-pel and fractional-pel search [6][7][8][9][10][11][12][13][14][15]. This approach requires separate reference-pixel buffers for each part.…”

Section: Introductionmentioning

confidence: 99%

“…The integerpel part usually applies the hierarchical strategies to extend the search range, which involves quality losses. Most architectures use non-adaptive search patterns and their resource consumption is large [6][7][8][9][10]. The architecture supporting Multipoint Diamond Search proposed in [11] requires less resource.…”

Section: Introductionmentioning

confidence: 99%

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Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

Pastuszak

Trochimiuk

2014

J Real-Time Image Proc

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This paper presents the architecture of the highthroughput compensator and the interpolator used in the motion estimation of the H.265/HEVC encoder. The architecture can process 898 blocks in each clock cycle. The design allows the random order of checked coding blocks and motion vectors. This feature makes the architecture suitable for different search algorithms. The interpolator embeds 64 multiplierless reconfigurable filter cores to support computations for different fractional-pel positions. Synthesis results show that the design can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively. The computational scalability enables the proposed architecture to trade the throughput for the compression efficiency. If 2160p@30fps video is encoded, the design clocked at 400 MHz can check about 100 motion vectors for 898 blocks.

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“…In particular, the wider range with the subsampling corresponds to the coarse resolution level. Typically, two [10], [12] or three [11], [13] levels are employed. All the architectures use non-adaptive search patterns and their resource consumption is large.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder

Pastuszak

Jakubowski

2013

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-Motion estimation is the most computationally intensive part of video encoders, as the compression efficiency usually increases with the amount of computations. The adaptive computationally scalable motion-estimation algorithm and its hardware implementation described in this paper allow the H.264/AVC encoders to achieve efficiencies close to optimal in real-time conditions. The algorithm employs several search strategies to adapt to local motion activity, and the number of checked search points is set by the encoder controller for each macroblock. The algorithm can achieve results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies over time. The architecture applies a novel dataflow. First, the motion vector generation is not constrained by the calculation of residuals and corresponding costs. Second, the fractional-pel interpolation is performed prior to the integer-pel search. Third, the ME and compensation use the same resources.

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HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

Cited by 79 publications

References 26 publications

An efficient interpolation filter VLSI architecture for HEVC standard

An efficient interpolation filter VLSI architecture for HEVC standard

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder

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