HDR-ARtiSt: High dynamic range advanced real-time imaging system

Abstract

This paper describes the HDR-ARtiSt hardware platform, a FPGA-based architecture that can produce a realtime high dynamic range video from successive image acquisition. The hardware platform is built around a standard low dynamic range (LDR) CMOS sensor and a Virtex 5 FPGA board. The CMOS sensor is a EV76C560 provided by e2v. This 1.3 Megapixel device offers novel pixel integration/readout modes and embedded image pre-processing capabilities including multiframe acquisition with various exposure times. Our approach consists of a hardware architecture with different algorithms: double exposure control during image capture, building of an HDR image by combining the multiple frames, and final tone mapping for viewing on a LCD display. Our video camera system is able to achieve a real-time video rate of 30 frames per second for a full sensor resolution of 1, 280 × 1, 024 pixels.

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

“…The summary presents the utilization of a single tone mapping block, and the full system which includes DDR2 and DVI controllers. As a comparison, the utilization summary from [13] is also given, since the same FPGA family is used. Our implementation instantiates more DSP blocks, which are used for multiplication, whereas utilization of all the other resources is significantly reduced.…”

“…can be a single HDR sensor streaming video signal [13] or a single LDR camera taking multiple shots under different exposure settings. In both cases, the Camera Interface outputs HDR images that are written to the memory.…”

“…A method with a lower number of bits reduces the precision and the dynamic range of the image. Lapray et al [13] presented a full imaging system with an FPGA as a processing core. Even though the used camera sensor streams 60 fps signal, the system provides only 30 fps output video for 1 Mpixel frame.…”

Scene-based non-uniformity correction: From algorithm to implementation on a smart camera

“…A second perspective is the implementation of this method in other FPGA smart cameras developed in our research group. We aim at implementing such a correction method to the HDR-ARtist platform [48] dedicated to high dynamic range imaging in order to achieve the best quality possible.…”

Multi-camera platform for panoramic real-time HDR video construction and rendering

“…This originates from the Gaussian pyramid and look-up table (LUT) implementation of the logarithm function [29] and a local Poisson solver [30]. Another FPGA system was implemented by Lapray et al [31,32]. They presented several full imaging systems on Virtex-5 FPGA platform as a processing core.…”