Hass

Shelepov, Daniel; Sáez, Juan Carlos; Jeffery, Stacey; Fedorova, Alexandra; Pérez, N.; Huang, Zhi Feng; Blagodurov, Sergey; Kumar, Viren

doi:10.1145/1531793.1531804

Cited by 186 publications

(11 citation statements)

References 18 publications

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“…Whereas these works provided novel mechanisms, these works did not consider energy-performance trade-offs with systems of high degree of heterogeneity or fine-grained configurations. Shelepov et al [27] proposed a heterogeneity-aware scheduler that dynamically maps applications to the best cores. However, the scheduler required an offline application architectural signature, in order to estimate the performance of an application on a core during runtime.…”

Section: Application Scheduling and Core Tuningmentioning

confidence: 99%

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Alsafrjalani

Gordon‐Ross

2018

Computers

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Heterogeneous and configurable multicore systems provide hardware specialization to meet disparate application hardware requirements. However, effective multicore system specialization can require a priori knowledge of the applications, application profiling information, and/or dynamic hardware tuning to schedule and execute applications on the most energy efficient cores. Furthermore, even though highly disparate core heterogeneity and/or highly configurable parameters with numerous potential parameter values result in more fine-grained specialization and higher energy savings potential, these large design spaces are challenging to efficiently explore. To address these challenges, we propose a novel configuration-subsetted heterogeneous and configurable multicore system, wherein each core offers a small subset of the design space, and propose a novel scheduling and tuning (SaT) algorithm to efficiently exploit the energy savings potential of this system. Our proposed architecture and algorithm require no a priori application knowledge or profiling, and incur minimal runtime overhead. Results reveal energy savings potential and insights on energy trade-offs in heterogeneous, configurable systems.

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Section: Application Scheduling and Core Tuningmentioning

confidence: 99%

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Alsafrjalani

Gordon‐Ross

2018

Computers

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“…In terms of HMP scheduling investigation, several studies examine whether it is possible to augment the architecture and make it more aware of the heterogeneity to exploit the bene ts of fast and low overhead migrations [24,29].…”

Section: Related Workmentioning

confidence: 99%

Nucleus

Vougioukas

Sandberg

Diestelhorst

et al. 2017

ACM Trans. Embed. Comput. Syst.

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Heterogeneous multi-processors are designed to bridge the gap between performance and energy e ciency in modern embedded systems. is is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation and latency masking, with In-Order (InO) cores, that preserve energy through simpler design. By leveraging migrations between them, workloads can therefore select the best se ing for any given energy/delay envelope. However, migrations introduce execution overheads that can hurt performance if they happen too frequently. Finding the optimal migration frequency is critical to maximize energy savings while maintaining acceptable performance. We develop a simulation methodology that can 1) isolate the hardware e ects of migrations from the so ware, 2) directly compare the performance of di erent core types, 3) quantify the performance degradation and 4) calculate the cost of migrations for each case. To showcase our methodology we run mibench, a microbenchmark suite, and show that migrations can happen as fast as every 100k instructions with li le performance loss. We also show that, contrary to numerous recent studies, hypothetical designs do not need to share all of their internal components to be able to migrate at that frequency. Instead, we propose a feasible system that shares level 2 caches and a translation lookaside bu er that matches performance and e ciency. Our results show that there are phases comprising up to 10% that a migration to the OoO core leads to performance bene ts without any additional energy cost when running on the InO core, and up to 6% of phases where a migration to the InO core can save energy without a ecting performance. When considering a policy that focuses on improving the energy-delay product, results show that on average 66% of the phases can be migrated to deliver equal or be er system operation without having to aggressively share the entire memory system or to revert to migration periods ner than 100k instructions. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage and that copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permi ed. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speci c permission and/or a fee. Request permissions from permissions@acm.org. Instructions per cycle Fig. 1. An excerpt of execution of dijkstra running on two di erent core types. Sampling at a higher resolution reveals phases that can potentially be exploited to increase e iciency. INTRODUCTIONIn today's embedded devices, performance is always tied to power constraints and energy e ciency. is happens because, while process technology scaling is enabling larger transistor densities, power per area has shown to increase beyond a certain thr...

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“…Hardware. The adopted experimental environment is similar to those used in prior work [15,26] in the domain of AMP. In those works, an AMP machine consists of two core types namely fast and slow cores.…”

Section: Evaluationsmentioning

confidence: 99%

“…[9,17,18,[21][22][23]26] aim at determining the best thread to core mapping in order to improve thread performance. [26] investigates applications which are composed of both parallel and sequential phases. [26] improves the scheduler by running sequential phase threads on fast cores.…”

Section: The Heterogeneity Issue In Amp Cloudsmentioning

confidence: 99%

Dealing with Performance Unpredictability in an Asymmetric Multicore Processor Cloud

Teabe

Wapet

Tchana

et al. 2017

Lecture Notes in Computer Science

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In a Cloud computing data center and especially in a IaaS (Infrastructure as a Service), performance predictability is one of the most important challenges. For a given allocated virtual machine (VM) in one IaaS, a client expects his application to perform identically whatever is the hosting physical server or its resource management strategy. However, performance predictability is very difficult to enforce in a heterogeneous hardware environment where machines do not have identical performance characteristics, and even more difficult when machines are internally heterogeneous as for Asymmetric Multicore Processor machines. In this paper, we introduce a VM scheduler extension which takes into account hardware performance heterogeneity of Asymmetric Multicore Processor machines in the cloud. Based on our analysis of the problem, we designed and implemented two solutions: the first weights CPU allocations according to core performance, while the second adapts CPU allocations to reach a given instruction execution rate (Ips) regardless the core types. We demonstrate that such scheduler extensions can enforce predictability with a negligible overhead on application performance.

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Hass

Cited by 186 publications

References 18 publications

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Nucleus

Dealing with Performance Unpredictability in an Asymmetric Multicore Processor Cloud

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