Hardware-Validated CPU Performance and Energy Modelling

Abstract

Full-system simulation frameworks such as gem5 are used extensively to evaluate research ideas and for designspace exploration. Moreover, energy-efficiency has become the key design constraint in recent years and many works use a separate power modelling framework to evaluate energy consumption. While such tools are convenient and flexible, they are known to contain sources of error which are often not fully understood and potentially impact the conclusions drawn from investigations. This work enables accurate, hardware-validated performance, power, and energy modelling of CPUs by first presenting a methodology to evaluate and identify sources of error in CPU performance models, and secondly developing empirical power models optimised for use with such performance models. Hierarchical clustering, correlation analysis, and regression techniques are used to identify sources of error without requiring detailed CPU specifications and enable existing models to be improved, new models to be developed, validation of simulator changes, and testing of model suitability for specific use-cases. Furthermore, the GemStone open-source software tool is presented, which automates the process of characterising hardware platforms, identifying sources of error in gem5 models, applying power analysis, and quantifying the effect of errors on the performance, power, and energy estimations. In addition, the mean percentage error in execution time was found to swing from −51% to +10% between two versions of the same gem5 model, underlining the need for an automated tool to validate models against reference hardware, ensuring accuracy and consistency.

NVIDIA GPGPUs Instructions Energy Consumption

“…Here, software is written to model hardware behaviour, mainly by abstracting signals and operations to function calls. It is not synthesizable, hence not a replacement for RTL, but it provides for fast simulation and prototyping, allowing reasonably accurate power and performance modelling of complex systems running complex software [15]. Power consumption can be estimated in gem5 by recording architectural events and feeding them to a power modelling tool [15].…”

Racing to Hardware-Validated Simulation

“…For this reason, Desikan et al [14] restricted their validation to the Alpha 21264 processor whose microarchitecture is disclosed in considerably more detail than other processors [24], [25]. This specification challenge (or lack thereof) triggered Walker et al [17] to propose a methodology to evaluate the sources of error in simulation relative to real hardware using the gem5 simulator and the configuration parameters that come with it. Their proposed methodology employs clustering and regression analysis to understand the relation between hardware and simulator performance events and their association to the error in performance.…”

“…Step #5 recommends performing an extra optimization round to focus on the modeling of a particular component. This step emphasizes the importance of accurately modeling all components and not relying only on a seemingly low error in overall performance estimation [16], [17]. For optimizations targeting a specific component, we recommend including metrics that are relevant to that component in the cost function of the tuning algorithm.…”

“…Our approach differs from recent work by Walker et al [17] which relies on clustering techniques to group applications with similar modeling error, and then clustering performancerelated events according to their impact on error. This is followed by regression analysis in an attempt to establish the relation between model error and a particular event, from which a candidate reason (or few reasons) for the modeling error can be identified.…”

“…Thus, simulator users resort to best-effort estimates or rely on dated processor information to fill the missing model parameters. In an attempt to limit the margin of simulation error and raise the confidence in their results, simulator users validate their models against real-world processors [14]- [17]. The increasing complexity and diversity in modern-day microprocessors calls for a systematic approach to validate simulators against processors of interest.…”