Hardware Transactions in Nonvolatile Memory

Abstract

International audienceHardware transactional memory (HTM) implementations already provide a transactional abstraction at HW speed in multi-core systems. The imminent availability of mature byte-addressable, nonvolatile memory (NVM) will provide persistence at the speed of accessing main memory. This paper presents the notion of persistent HTM (PHTM), which combines HTM and NVM and features hardware-assisted, lock-free, full ACID transactions. For atomicity and isolation, PHTM is based on the current implementations of HTM. For durability, PHTM adds the algorithmic and minimal HW enhancements needed due to the incorporation of NVM. The paper compares the performance of an implementation of PHTM (that emulates NVM aspects) with other schemes that are based on HTM and STM. The results clearly indicate the advantage of PHTM in reads, as they are served directly from the cache without locking or versioning. In particular, PHTM is an order of magnitude faster than the best persistent STM on read-dominant workloads

Persistency semantics of the Intel-x86 architecture

“…This coarse-grained atomicity abstraction simplifies correct concurrent programming. As such, NVM researchers have sought to extend atomicity guarantees of transactions to persistency: upon recovery, either all or none of the writes of a transactions may have persisted [Avni et al 2015;Intel 2015;Shu et al 2018;Tavakkol et al 2018].…”

“…Nevertheless, their semantic models are low-level, rendering them too complex for the inexperienced developers. The NVM community has thus moved towards high-level transactional approaches [Avni et al 2015;Intel 2015;Shu et al 2018;Tavakkol et al 2018], such as our PSER library in Px86.…”

Hardware transactional persistent memory

“…Solutions like using an atomic counter within transactions to order them correctly are not practical since the shared counter will result in HTM-induced aborts and serialization of all transactions. Some papers have advocated that processor manufacturers alter HTM semantics and implementation to allow selective writes to PM from within an HTM [13,21,22]. We describe our solution without the need for such intrusive processor changes in Section 3.…”

“…However, all of these solutions require making signi cant changes to the existing HTM semantics and implementations. For instance, PHTM [21] and PHyTM [22], propose a new instruction called TransparentFlush which can be used to ush a cache line from within a transaction to persistent memory without causing any transaction to abort. ey also propose a change to the xend instruction that ends an atomic HTM region, so that it atomically updates a bit in persistent memory as part of its execution.…”

“…For these, PTM [20] proposes changes to processor caches while adding an on-chip scoreboard and global transaction id register to couple HTM with PM. Recent work [13,21,22] has a empted to provide inter-transactional isolation by employing processor based (HTM) [7,8] mechanisms. However, these solutions all require changes to the existing HTM semantics and implementations- [21] and [22] propose a new instruction to perform non-aborting cacheline ush from within an HTM, while [13] proposes allowing non-aborting concurrent access to designated memory variables within an HTM. Selective and incremental changes to the clean isolation semantics of HTM are not to be undertaken lightly; understanding their impact on global system correctness and performance typically requires long gestation periods before processor manufacturers will embrace them.…”