Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach

Microprocessors and Microsystems

Rubattu

et al. 2021

Self Cite

Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches. This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with.

“…The contributions of this paper, and more in general what is new in the MDC tool with respect to [7], are reported hereinafter.…”

Section: Contribution Of the Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Microprocessors and Microsystems

Rubattu

et al. 2021

Self Cite

“…Concepts as FPGA overlays and FPGA companion computers are nowadays extremely popular [9,43]. They are addressed in many studies that target HW/SW systems [20,32,36] that aim to couple microprocessors with HW accelerators, which may also offer different levels of reconfigurability [14]. This introduces the need for having visibility at various levels of the computing infrastructure.…”

Section: Monitoring Heterogeneous Systems: Context and Backgroundmentioning

confidence: 99%

“…The I/O Manager is responsible of transferring the input data to the computing core of the coprocessor, which is the Data Cruncher, and to collect from it the results that will be transferred back to the host microprocessor through the Transaction Handler. Such a generic coprocessor architecture is quite common and it is adopted by different FPGA based computing heterogeneous platforms that embed coprocessing units [20,32,36]. In such architectures three monitoring levels are possible:…”

Section: Implementation and Programmability Detailsmentioning

confidence: 99%

A Composable Monitoring System for Heterogeneous Embedded Platforms

Valente

ACM Trans. Embed. Comput. Syst.

et al. 2021

Self Cite

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

“…In general, the research activity in this context is flourishing [2]- [8]. In the H2020 CERBERO 1 European Project [8] we worked on providing a continuous design environment for CPSs that, at computational level, relies on many tools for FPGA-based CPSs, which have been accessed during the project time-frame on a Planetary Exploration use-case [9]. An adaptive embedded controller for a robotic manipulator has been implemented over an FPGA.…”

Section: Introductionmentioning

confidence: 99%

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Rubattu

et al. 2020

IEEE Access

Self Cite

Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part of the computing infrastructure, to better shape the execution on the application needs/features, and offer high efficiency in terms of timing and power performance, while naturally featuring parallelism. In the context of FPGA-based CPSs, this paper has a two fold mission. On the one hand, it presents an analysis of the Damped Least Square (DLS) algorithm for a perspective hardware implementation. On the other hand, it describes the implementation of a robotic arm controller based on the DLS to numerically solve Inverse Kinematics problems over a heterogeneous FPGA. Assessments involve a Trossen Robotics WidowX robotic arm controlled by a Digilent ZedBoard provided with a Xilinx Zynq FPGA that computes the Inverse Kinematic.