Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder

Khan, Muhammad Usman; Shafique, Muhammad; Grellert, Mateus; Henkel, Jörg

doi:10.7873/date.2013.039

Cited by 35 publications

(23 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Following the same reasoning, the expression of the colines with orientation r 2 is obtained by isolating for the variable c 2 from (8) and substituting it into (9), as is shown in (10) and (11)…”

Section: Sub-sampling Of Integer Latticementioning

confidence: 99%

“…The variance is computed along the co-lines according to (8)- (11), instead of using the digital lines expression. 2.…”

Section: Computation Of Mean Directional Variance (Mdv) Along Co-linesmentioning

confidence: 99%

“…With the aim of achieving the best intra-coding performance, an exhaustive evaluation of the whole number of possible CU, PU and TU sizes and the full number of available prediction modes is carried out by using a well-known Rate Distortion Optimization (RDO) technique [8]. While such flexibility leads to high compression efficiency, it comes at the expenses of a huge computational burden, primarily due to the large number of available directional predictors and PU sizes [9], which is hindering the rapid adoption of HEVC by the professional market [10,11].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A unified architecture for fast HEVC intra-prediction coding

Ruiz

Fernández–Escribano

Martínez

et al. 2017

J Real-Time Image Proc

View full text Add to dashboard Cite

The high efficiency video coding (HEVC) is the new video coding standard, which obtains over 50% bit rate savings compared with H.264/AVC for the same perceptual quality. Intra-prediction coding in HEVC achieves high coding performance in expense of high computational complexity, due to the exhaustive evaluation of all available coding units (CU) sizes, with up to 35 prediction modes for each CU, selecting the one with the lower rate distortion cost, among other new features. This paper presents a Unified Architecture to form a novel fast HEVC intra-prediction coding algorithm, denoted as fast partitioning and mode decision. This approach combines a fast partitioning decision algorithm, based on decision trees, which are trained using machine learning techniques, and a fast mode decision algorithm, based on a novel texture orientation detection algorithm, which computes the mean directional variance along a set of co-lines with rational slopes using a sliding window over the prediction unit. Both algorithms proposed apply a similar approach, exploiting the strong correlation between several image features and the optimal CTU partitioning and the optimal prediction mode. The key point of the combined approach is that both algorithms compute the image features with low complexity, and the partition decision and the mode decision can also be taken with low complexity, using decision trees (if-else statements) and by selecting the minimum directional variance between a reduced set of directions. This approach can be implemented using any combination of nodes, obtaining a wide range of time savings, from 44 to 67%, and light penalties from 1.1 to 4.6%. Comparisons with similar state-of-the-art works show the proposed approach achieves the best trade-off between complexity reduction and rate distortion.

show abstract

Section: Sub-sampling Of Integer Latticementioning

confidence: 99%

“…The variance is computed along the co-lines according to (8)- (11), instead of using the digital lines expression. 2.…”

Section: Computation Of Mean Directional Variance (Mdv) Along Co-linesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A unified architecture for fast HEVC intra-prediction coding

Ruiz

Fernández–Escribano

Martínez

et al. 2017

J Real-Time Image Proc

View full text Add to dashboard Cite

show abstract

“…Area of the proposed FPGA implementation is smaller than the ones proposed in [8]- [12]. Power consumptions of the HEVC intra prediction hardware proposed in [9]- [12] are not reported. The proposed FPGA implementation consumes less power than the one proposed in [8].…”

Section: Proposed Hevc Intra Prediction Hardwarementioning

confidence: 99%

“…Frames per second performance of the HEVC intra prediction hardware proposed in [12] is not reported. Since the HEVC intra prediction hardware in [10] is proposed for an HEVC decoder, its frames per second performance for an HEVC encoder is not reported.…”

Section: Proposed Hevc Intra Prediction Hardwarementioning

confidence: 99%

An efficient FPGA implementation of HEVC intra prediction

Azgın

Mert

Kalalı

et al. 2018

2018 IEEE International Conference on Consumer Electronics (ICCE)

View full text Add to dashboard Cite

Abstract-Intra prediction algorithm used in High EfficiencyVideo Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4x4, 8x8, 16x16 and 32x32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920x1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

show abstract