Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme

Abstract

Power dissipation has become a critical design constraint for the growth of modern multicore systems due to increasing clock frequencies, leakage currents, and system parasitics. To overcome this urgent crisis, this article presents an embedded platform for on-chip power management of a multicore System-on-Chip (SoC). The design involves the development of two key components, from the hardware to the software level. From the hardware perspective, a multiple-supply power management unit is proposed and is implemented using a Single-Inductor Multiple-Output (SIMO) DC-DC converter. To dynamically respond to the sensed instantaneous power demands and to accurately control the power delivery to the processor cores, the power management unit employs a software-defined adaptive global/local power allocation feedback controller. The proposed controller is designed using the hardware-software codesign methodology to uniquely control the SIMO converter during various operation scenarios. This is achieved using several embedded software control algorithms that operate synergetically to ensure efficient and reliable system operation. The hardware-software codesign technique also allows the SIMO controller to be integrated with future microprocessor cores. Therefore, by employing the vast amount of on-chip resources, the converter can perform effective power processing to provide the most power-optimal voltages at the hardware level. Such an embedded power management module leads to an integrated, power-aware, and autonomous SoC design that is independent of additional external hardware control, thereby reducing on-chip area and system complexity. In this design, each power output from the SIMO converter provides a step-up/down voltage conversion, thereby enabling a wide range of variable supply voltage. An adaptive global/local power allocation control algorithm is employed to significantly improve Dynamic Voltage and Frequency Scaling (DVFS) tracking speed and line/load regulation, while still retaining low cross-regulation. Designed with a 180nm CMOS process, the converter precisely provides three independently variable power outputs from 0.9 V to 3.0 V, with a total power range from 33 mW to 900 mW. A very fast load transient response of 3.25 μs is achieved, in response to a 67.5-mA full-step load current change. The design thus provides a cost-effective power management solution to achieve a robust, fast-transient, DVFS-compatible multicore SoC.

Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor

“…Though 3D integration is one promising solution [3] to increase integration density and communication bandwidth, the provision of many-core power supply voltages with maintenance of low power density has become an unresolved issue to address [4,5,6,7,8]. Supplying same voltage-level to all cores will result in high power density because the demand of each core can be different at different time instant.…”

“…From physical hardware perspective, an optimal demand-supply matching requires on-chip power converters [5,6,7,8], which can provide prompt DVFS management with efficient power delivery. However, one power converter for one core has large area overhead in presence of non-scalable buck inductor.…”

“…However, one power converter for one core has large area overhead in presence of non-scalable buck inductor. The design of single-inductor-multiple-output (SIMO) power converters [6] utilizes one common single buck inductor to provide different voltage-levels at different time slots in a time-multiplexed manner. The capability of SIMO is, however, still limited for many-core microprocessors at thousand-core scale.…”

“…Moreover, there are many microprocessor cores but limited power converters. A number of power management works for many-core microprocessor system have been explored before [5,6,7,8] but with not fully resolved challenge that requires to not only match various demands from microprocessors with limited number of power converters, but also to reduce peak power and to balance workload on a power converter. As such, the smart power management of many-core microprocessor has similarity as smart-grid though at different time-scale with different workload behaviors.…”

2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

“…Power management techniques are often hindered by the offchip power converters, which adjusts voltage/frequency levels at a scale of few microsecond time-scale, which is inefficient. On-chip power converters [82,7,63,4,83,64,84,49,85] can provide fast switching time to different voltage levels compared to off-chip power converters. On-chip power converters can provide granularity of nanosecond time scale for power management, compared to micro-second granularity by off-chip power converter.…”