Hardware–software co-simulation of bus-based reconfigurable systems

Vikram, Karimella; Vasudevan, V.

doi:10.1016/j.micpro.2004.07.004

Cited by 7 publications

(5 citation statements)

References 25 publications

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“…. (16) Among these, the last equation is the most restrictive, since values monotonically decrease with . Also, since a gap occurs after load transfer to , we have (17) From (16) and 17, we can see that .…”

Section: A Without Front-endmentioning

confidence: 99%

“…(16) Among these, the last equation is the most restrictive, since values monotonically decrease with . Also, since a gap occurs after load transfer to , we have (17) From (16) and 17, we can see that . Since the load fractions are monotonically decreasing, we also have (18) To ensure minimum possible processing time, load transfer to must start immediately after configuration.…”

Section: A Without Front-endmentioning

confidence: 99%

“…The value of in (26) can be obtained as follows. The reconfiguration time must satisfy (16) and (17). Therefore, we can combine (16) and (17) to get (28) Let us now consider the inequality (29) where .…”

Section: A Without Front-endmentioning

confidence: 99%

“…1. Architecture model used for analysis of the hybrid processor architecture (a modified version of that presented in [16]). The block "GPP" includes the main processor as well as its associated cache.…”

Section: Introductionmentioning

confidence: 99%

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Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Vikram¹,

Vasudevan

2006

IEEE Trans. VLSI Syst.

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Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this paper, we present a methodology to map data-parallel tasks onto hardware that supports partial reconfiguration. The aim is to obtain the maximum possible speedup, for a given reconfiguration time, bus speed, and computation speed. The proposed approach involves using multiple, identical but independent processing units in the reconfigurable hardware. Under nonzero reconfiguration overhead, we show that there exists an upper limit on the number of processing units that can be employed beyond which further reduction in execution time is not possible. We obtain solutions for the minimum processing time, the corresponding load distribution, and schedule for data transfer. To demonstrate the applicability of the analysis, we present the following: 1) various plots showing the variation of processing time with different parameters; 2) hardware simulations for two examples, viz., 1-D discrete wavelet transform and finite impulse response filter, targeted to Xilinx field-programmable gate arrays (FPGAs); and 3) experimental results for a hardware prototype implemented on a FPGA board.

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Section: A Without Front-endmentioning

confidence: 99%

Section: A Without Front-endmentioning

confidence: 99%

Section: A Without Front-endmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Vikram¹,

Vasudevan

2006

IEEE Trans. VLSI Syst.

Self Cite

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“…Furthermore, this simulator does not support the feature of dynamic reconfiguration. Vikram and Vasudevan designed a behavior simulator for hardware-software co-simulation of reconfigurable systems [7]. This tool is a hybrid system in which the reconfigurable array is designed by Verilog HDL and the micro-controller is implemented by integrating RSIM [8] -a Cbased micro-processor simulator.…”

Section: Introductionmentioning

confidence: 99%

Design of a Simulator for Mesh-Based Reconfigurable Architectures

Sun

Zheng

et al. 2007

Lecture Notes in Computer Science

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Abstract.Reconfigurable computing has become a hot topic in research due to its high-performance and flexibility. In this paper we present a simulator called JRSim for mesh-based reconfigurable architectures. The purpose of this simulator is to provide a platform to evaluate new architectures, and to assist in analysis of algorithms as well as the visualization of their behavior. JRSim is a platform-independent tool which is implemented by Java. It supports flexible bus structure, user-defined function unit and dynamic reconfiguration. Case studies show that JRSim can simulate the behavior of mesh-based reconfigurable systems correctly and efficiently. This simulator can be used to evaluate reconfigurable system design, or demonstrate the ability of reconfigurable system in an educational environment.

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A Bumpless Switching Scheme for Dynamic Reconfiguration

Liu

Yan

2007

Lecture Notes in Computer Science

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Hardware–software co-simulation of bus-based reconfigurable systems

Cited by 7 publications

References 25 publications

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Design of a Simulator for Mesh-Based Reconfigurable Architectures

A Bumpless Switching Scheme for Dynamic Reconfiguration

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