Hardware–Software Co-Optimization of Long-Latency Stochastic Computing

Aygun, Sercan; Kouhalvandi, Lida; Najafi, M. Hassan; Ozoguz, Serdar; Gunes, Ece Olcay

doi:10.1109/les.2023.3298734

Cited by 2 publications

(1 citation statement)

References 18 publications

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“…For the former, evaluations in field programmable gate array (FPGA) or chip implementations have exhibited better performance than conventional binary logic and more reduced hardware resources [6][7][8][9]. For example, novel logic gate models and size optimization studies were conducted to solve the increased latency and power consumption caused by long bitstreams [10]. In addition, studies have been conducted on neurochips [11], novel subtraction, and activation functions [12], and weight updating using physical devices [13].…”

Section: Stochastic Computing and Memorymentioning

confidence: 99%

Stochastic memory device based on a bistable system model with a simple analog circuit

Muramatsu,

Nishida,

Ando

et al. 2024

NOLTA

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In recent years, artificial intelligence (AI) has attracted attention for edge AI, which operates in an offline environment without using clouds and focuses on the speed of responsiveness. Devices for this purpose must be power efficient and compact, and various methods have been studied to implement AI in hardware. In this context, an approximate computation method called stochastic computing (SC) can implement multiplication and addition, which are frequently used in AI computations with low resources, and are suitable for parallel processing. However, SC-based AI hardware implementations have problems with the use of conventional memory. To solve this problem, we propose a stochastic memory (SM) model based on a bistable system and simple analog circuit. We evaluate the SM characteristics using SPICE simulations and experiments using actual ICs. This is expected to enable the implementation of a combination of SM and AI hardware using SC from previous studies that are more suitable for edge AI requirements.

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