Hardware/software co-designed accelerator for vector graphics applications

Chen, Shuo-Hung; Lin, Hsiao-Mei; Wei, Hsin-Wen; Chen, Yi-Cheng; Huang, Chih-Tsun; Chung, Yeh‐Ching

doi:10.1109/sasp.2011.5941088

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…But because 2D and 3D interfaces are not unified, it is difficult to achieve it. Rendering is the most time-consuming step [5] to draw 2D vector graphics, and the current optimization for it focuses on the following aspects: optimization of rendering processes [8], partial rendering, efficient vector graphics filling algorithm [5] and hardware accelerating [9][10] [11].…”

Section: Related Workmentioning

confidence: 99%

The Rendering Optimization of SVG Player on Mobile Devices

Qiu¹,

Luo²,

Zhang³

2012

JDCTA

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With the 3G development, more and more rich media applications appear on mobile devices. The efficiency of scalable vector graphics player is very crucial for constrained mobile devices. In this paper, we propose a partial rendering algorithm which dynamically traces the invalid areas of elements in the scene and rationally divides the scene into several partial rendering areas. Compared with the traditional algorithms, this algorithm can obviously improve performance on high resolution mobile devices. We also present a new contour algorithm for fitting circular arc, which uses midpoint rule to calculate the control points of cubic bezier curve. This algorithm has lower complexity than the traditional algorithms and is suitable for arc drawing on mobile devices. The test results show that above two algorithms have good effect on rendering optimization.

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Section: Related Workmentioning

confidence: 99%

The Rendering Optimization of SVG Player on Mobile Devices

Qiu¹,

Luo²,

Zhang³

2012

JDCTA

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“…The third section represents an overview of the main developments regarding automatic hardware generators for FPGA. (Chen, 2011) (Mahdavikhah, 2010) (Majer, 2008). Regarding commercial IPs, these include the logicBricks 2D/3D graphics engines (logicBricks, 2011) and the D/AVE 3D graphic IP (TES, 2009).…”

Section: Introductionmentioning

confidence: 99%

Automatic Generation of Fpga Hardware Accelerators for Graphics Applications

Amăricăi

Boncalo

2012

Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems

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In recent years, FPGAs have been increasingly utilized in implementing graphic engines in application fields such as automotive, avionics or military. However, due to their high flexibility, designs for FPGA devices can target a very limited range of applications. In this paper, we discuss the opportunity of developing automatic generation tools for customized graphics hardware. These tools should generate an almost optimized RTL code only for the series of the required graphics operations of the specific application. 2 FPGA IMPLEMENTATIONS OF GRAPHIC ENGINES Several implementations for FPGA based acceleration of graphic engines have been developed 383

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