Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm

Abstract

Somewhat Homomorphic Encryption (SHE) schemes allow to carry out operations on data in the cipher domain. In a cloud computing scenario, personal information can be processed secretly, inferring a high level of confidentiality. For many years, practical parameters of SHE schemes were overestimated, leading to only consider the FFT algorithm to accelerate SHE in hardware. Nevertheless, recent work demonstrates that parameters can be lowered without compromising the security [1]. Following this trend, this work investigates the benefits of using Karatsuba algorithm instead of FFT for the Fan-Vercauteren (FV) Homomorphic Encryption scheme. The proposed accelerator relies on an hardware/software co-design approach, and is designed to perform fast arithmetic operations on degree 2560 polynomials with 135 bits coefficients, allowing to compute small algorithms homomorphically. Compared to a functionally equivalent design using FFT, our accelerator performs an homomorphic multiplication in 11.9 ms instead of 15.46 ms, and halves the size of logic utilization and registers on the FPGA.

FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data

“…In the literature there are several reported hardware implementation that try to speedup performance of HE schemes [11,12,13,14,15,16,17,18,19,20,21]. Several of these reported implementations report only simulation based results.…”

A Memory-Reinforced Tabu Search Algorithm With Critical Path Awareness for HW/SW Partitioning on Reconfigurable MPSoCs

“…This paper proposes a memory-reinforced tabu search algorithm applied to the partitioning problem P. A good initial solution can effectively improve the quality of the final solution of the TS algorithm, we use the solution generated in HA as the initial solution of MTS, and MTS maintains a tabu list with a maximum length of l that stores the forbidden movement. Considering that the partition solution in P is a sequence containing only 0 and 1, the movement S c can be formulated as (11), let S local denote solution for the current iteration, and S local denote the solution for last iteration. (11) The tabu list can prohibit l types of movement in the current iteration, and the tabu list is the FIFO queue.…”

“…Considering that the partition solution in P is a sequence containing only 0 and 1, the movement S c can be formulated as (11), let S local denote solution for the current iteration, and S local denote the solution for last iteration. (11) The tabu list can prohibit l types of movement in the current iteration, and the tabu list is the FIFO queue. Whenever a new value is stored, the earliest stored value will be released.…”

“…Efficient techniques for HW/SW co-design [9]- [11] are necessary to realize embedded systems that must meet design constraints while satisfying the shorter time-to-market pressures [12]. HW/SW partitioning [9], [13], [14] is the crucial step during HW/SW co-design, and the HW/SW partitioning algorithm determines which components are implemented in hardware and which components are implemented in software [15].…”

A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm

“…In practice, few approaches use hardware to target homomorphic encryption with batching for binary messages due to the incompatibility with NTT. To our knowledge, only [14] and [15] provide complete accelerators with batching, although the former focuses on the server side only and the latter only targets complex homomorphic algorithms. In this paper, we provide the first batching compliant implementation of homomorphic encryption on the client side using the Karatsuba algorithm [16], and compare our results to the latest homomorphic libraries.…”