Hardware-software co-design of AES on FPGA

Baskaran, S.; Rajalakshmi, P.

doi:10.1145/2345396.2345575

Cited by 8 publications

(8 citation statements)

References 11 publications

(7 reference statements)

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“…The number of rounds depends on the length of the key used for the encryption process. The Advanced Encryption Standard can be programmed in software or built with pure hardware [8].…”

Section: A Aes Encryptionmentioning

confidence: 99%

VHDL implementation of AES-128 on FPGA

Chavan¹,

Annadate²

2015

International Journal of Innovative Research in Electrical, Ele

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Abstract:The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last few years. A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. The design has been coded by Very high speed integrated circuit Hardware Descriptive Language. All the results are synthesized and simulated using Xilinx ISE and ModelSim software respectively. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.

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“…The number of rounds depends on the length of the key used for the encryption process. The Advanced Encryption Standard can be programmed in software or built with pure hardware [8].…”

Section: A Aes Encryptionmentioning

confidence: 99%

VHDL implementation of AES-128 on FPGA

Chavan¹,

Annadate²

2015

International Journal of Innovative Research in Electrical, Ele

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“…It is based on consistency with some mathematical proof. Non-repudiation in cryptology means that it can be verified that the sender and the recipient were, in fact, the parties who claimed to send or receive the message, respectively [5]. The main Aim of presented AES design is to present mathematical models for the AES algorithm which reduces the hardware Implementations cost.…”

Section: Aim Of the Papermentioning

confidence: 99%

“…At backbone communication channels or heavily loaded servers it is not possible to lose processing speed, which drops the efficiency of the overall system while running cryptography algorithms in software [5]. On the other hand, in the performance comparison between software and hardware implementation the priority is to evaluate which system provides higher security.…”

Section: Encryption and Decryption In Aesmentioning

confidence: 99%

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Shared Architecture for Encryption/Decryption of AES

KumariSharma¹,

Biradar²,

Singh³

2013

IJCA

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Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is based on the Rijndael algorithm. Here this paper presents the shared architectures for both encryption and decryption. Shared architecture reduces the area as well as the path delay. This methodology uses VHDL implementation of all the modules and results are concluded in terms of Delay and Frequency.

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“…The core library of OpenSSL implements basic cryptographic functions and provides various utility functions. However, its crypto functions, such as symmetric key ciphers and hash algorithms, are extremely compute-intensive operations [6,7]. OpenSSL does these expensive computations through software implementations and it may not be able to compete with the increasing need for speed and secure connections for web services [8].…”

Section: Introductionmentioning

confidence: 99%

Hardware/Software Adaptive Cryptographic Acceleration for Big Data Processing

Xiao

Zhang

Liu

2018

Security and Communication Networks

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Along with the explosive growth of network data, security is becoming increasingly important for web transactions. The SSL/TLS protocol has been widely adopted as one of the effective solutions for sensitive access. Although OpenSSL could provide a freely available implementation of the SSL/TLS protocol, the crypto functions, such as symmetric key ciphers, are extremely compute-intensive operations. These expensive computations through software implementations may not be able to compete with the increasing need for speed and secure connection. Although there are lots of excellent works with the objective of SSL/TLS hardware acceleration, they focus on the dedicated hardware design of accelerators. Hardly of them presented how to utilize them efficiently. Actually, for some application scenarios, the performance improvement may not be comparable with AES-NI, due to the induced invocation cost for hardware engines. Therefore, we proposed the research to take full advantages of both accelerators and CPUs for security HTTP accesses in big data. We not only proposed optimal strategies such as data aggregation to advance the contribution with hardware crypto engines, but also presented an Adaptive Crypto System based on Accelerators (ACSA) with software and hardware codesign. ACSA is able to adopt crypto mode adaptively and dynamically according to the request character and system load. Through the establishment of 40 Gbps networking on TAISHAN Web Server, we evaluated the system performance in real applications with a high workload. For the encryption algorithm 3DES, which is not supported in AES-NI, we could get about 12 times acceleration with accelerators. For typical encryption AES supported by instruction acceleration, we could get 52.39% bandwidth improvement compared with only hardware encryption and 20.07% improvement compared with AES-NI. Furthermore, the user could adjust the trade-off between CPU occupation and encryption performance through MM strategy, to free CPUs according to the working requirements.

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Hardware-software co-design of AES on FPGA

Cited by 8 publications

References 11 publications

VHDL implementation of AES-128 on FPGA

VHDL implementation of AES-128 on FPGA

Shared Architecture for Encryption/Decryption of AES

Hardware/Software Adaptive Cryptographic Acceleration for Big Data Processing

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