Hardware/software co-design for energy-efficient seismic modeling

Abstract

Reverse Time Migration (RTM) has become the standard for high-quality imaging in the seismic industry. RTM relies on PDE solutions using stencils that are 8 t h order or larger, which require large-scale HPC clusters to meet the computational demands. However, the rising power consumption of conventional cluster technology has prompted investigation of architectural alternatives that offer higher computational efficiency. In this work, we compare the performance and energy efficiency of three architectural alternatives -the Intel Nehalem X5530 multicore processor, the NVIDIA Tesla C2050 GPU, and a general-purpose manycore chip design optimized for high-order wave equations called "Green Wave." We have developed an FPGA-accelerated architectural simulation platform to accurately model the power and performance of the Green Wave design. Results show that across highly-tuned high-order RTM stencils, the Green Wave implementation can offer up to 8× and 3.5× energy efficiency improvement per node respectively, compared with the Nehalem and GPU platforms. These results point to the enormous potential energy advantages of our hardware/software co-design methodology.

Collective Memory Transfers for Multi-Core Chips

“…We then present application results for the following important stencil-based applications: fluid animation from the PARSEC benchmark suite [6], geometric multi-grid calculations (GMG) [73], seismic wave propagation simulation (RTM) [46], the SOBEL filter used extensively for image processing [23], and a collection of Laplacian stencil kernels [35]. For the application results, we model Intel Phi co-processors, which are simple x86-based processors and representative of the simple cores projected for future many-core chips [9,68].…”

“…To illustrate the benefits of CMS, we focus on stencil algorithms because of their broad applicability, the memory bandwidth sensitivity of their kernels [36,18,12,1], and their ubiquitous usage [55]. In particular, stencil algorithms constitute a large fraction of consumer, embedded, HPC and scientific applications in such diverse areas as image processing, seismic imaging [46], heat diffusion, electromagnetics, fluid dynamics, and climate modeling [51,52,78,56]. These applications often use iterative finite-difference techniques, which sweep over a spatial grid, performing nearest neighbor computations called stencils.…”

“…Past work has repeatedly reported that a wide variety of applications are constrained by memory bandwidth [65,28,64,59,36,18,46,12,32,55]. In those cases, while local and last-level caches can eliminate DRAM accesses during the computation phase of a loop, data is still retrieved from main memory when loading new and storing old HTAs, which is the focus of CMS.…”

“…In addition, while memory density nearly doubles every two years, the improvement in cycle time has been hundreds of times less, leading to tens to hundreds of processor cycles per memory access; this limits performance in latency-sensitive systems [10,48]. Examples of data-parallel memory bandwidth-bound applications include the Laplacian and wave equations stencil kernel (used in a variety of applications such as seismic simulation [46]), combustion simulation [12], face recognition [38], image processing [1], fluid simulation [53], embedded applications [75,45], and many others [36,18,12,1]. Media applications have also been reported to require up to 300GB/s of bandwidth to utilize just 48 processors [57].…”

“…Examples include sparse and dense linear algebra kernels, FFTs used in spectral methods for filtering, stencil kernels for image processing and seismic imaging [46], and fluid dynamics simulation [12,53]. Bulk-synchronous kernels typically rely on domain decomposition to expose data parallelism.…”