Hardware selection and clustering in the HYPER synthesis system

Abstract

A novel approach for ihe hardware seleciion and clusienng problem an high leeel synthesrs is presented The goal of the hardware seleciion is io select a set of hardware modules which minimize ihe rmplemeniaiion cosi of an algorithm, given ihe timing and ihroughpui condrainis. Ai ihe same iime, simple operaiors are clusiered inio large combinaional blocks io reduce ihe regisier count and io incrtase ihe ihroughpui. The proposed approach is organized as a search employing a relazed schedulrng for cost estimation and uses a simple, yet accurate timing analysis to cerify timzng constraints The resulis from real applicaiions showed the ezcellent performance of ihe proposed algorithm