Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V

Nicholas, Geraldine Shirley; Thakar, Bhavin; Saqib, Fareena

doi:10.1145/3453688.3461517

Cited by 1 publication

(1 citation statement)

References 55 publications

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“…The loads are encoded in I-type format, and the store instructions are encoded in S-type format. Two new instructions are added to the ISA, which is used to provide security checks for the 1-bit tag in the tag mechanism [44]. Based on the load and store encoding specified in the RISC-V core, the new instructions are as follows:…”

Section: Risc-vmentioning

confidence: 99%

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V

Nicholas,

Aklekar,

Thakar

et al. 2023

Cryptography

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With the proliferation of electronic devices, third-party intellectual property (3PIP) integration in the supply chain of the semiconductor industry and untrusted actors/fields have raised hardware security concerns that enable potential attacks, such as unauthorized access to data, fault injection and privacy invasion. Different security techniques have been proposed to provide resilience to secure devices from potential vulnerabilities; however, no one technique can be applied as an overarching solution. We propose an integrated Information Flow Tracking (IFT) technique to enable runtime security to protect system integrity by tracking the flow of data from untrusted communication channels. Existing hardware-based IFT schemes are either fine-, which are resource-intensive, or coarse-grained models, which have minimal precision logic, providing either control-flow or data-flow integrity. No current security model provides multi-granularity due to the difficulty in balancing both the flexibility and hardware overheads at the same time. This study proposes a multi-level granularity IFT model that integrates a hardware-based IFT technique with a gate-level-based IFT (GLIFT) technique, along with flexibility, for better precision and assessments. Translation from the instruction level to the data level is based on module instantiation with security-critical data for accurate information flow behaviors without any false conservative flows. A simulation-based IFT model is demonstrated, which translates the architecture-specific extensions into a compiler-specific simulation model with toolchain extensions for Reduced Instruction Set Architecture (RISC-V) to verify the security extensions. This approach provides better precision logic by enhancing the tagged mechanism with 1-bit tags and implementing an optimized shadow logic that eliminates the area overhead by tracking the data for only security-critical modules.

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Section: Risc-vmentioning

confidence: 99%