Hardware schemes for early register release

Monreal, Teresa; Viñals, Víctor; González, Antonio; Valero, Mateo

doi:10.1109/icpp.2002.1040854

Cited by 34 publications

(60 citation statements)

References 26 publications

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“…Delayed physical register allocation was also used in [17] to reduce the conflicts over the write ports in a multiple-banked register file. The second set of techniques aim at reducing the register file pressure by using the early deallocation of physical registers [14,15,16,24,41,45]. In [46], a combination of early deallocation and late allocation was used to completely avoid register allocation for a large number of instructions.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure

Ergin¹,

Balkan

Ghose

et al.

37th International Symposium on Microarchitecture (MICRO-37'04)

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Section: Related Workmentioning

confidence: 99%

“…Researchers have generally exploited the inefficiencies in register usage to reduce the number of registers by using late register allocation [7,19,33], early deallocation [14,15,16,24] and register sharing [4,11,18]. In this paper, we propose alternative mechanisms for reducing the register file pressure.…”

Section: Introductionmentioning

confidence: 99%

Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure

Ergin¹,

Balkan

Ghose

et al.

37th International Symposium on Microarchitecture (MICRO-37'04)

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show abstract

“…This logic is generally arranged in table format to provide predictions for the future [Butts and Sohi 2004] or to accumulate knowledge for use later in the pipeline [Monreal et al 2002]. Supplementing the microarchitecture in this way increases the processor's energy budget, offsetting any performance gains achieved.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient register caching with compiler assistance

Jones

O’Boyle

Abella

et al. 2009

ACM Trans. Archit. Code Optim.

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The register file is a critical component in a modern superscalar processor. It must be large enough to accommodate the results of all in-flight instructions. It must also have enough ports to allow simultaneous issue and writeback of many values each cycle. However, this makes it one of the most energy-consuming structures within the processor with a high access latency. As technology scales, there comes a point where register accesses are the bottleneck to performance and so must be pipelined over several cycles. This increases the pipeline depth, lowering performance.To overcome these challenges, we propose a novel use of compiler analysis to aid register caching. Adding a register cache allows us to preserve single-cycle register accesses, maintaining performance and reducing energy consumption. We do this by passing information to the processor using free bits in a real ISA, allowing us to cache only the most important registers. Evaluating the register cache over a variety of sizes and associativities and varying the read ports into the cache, our best scheme achieves an energy-delay-squared (EDD) product of 0.81, with a performance increase of 11%. Another configuration saves 13% of register system energy. Using four register cache read ports brings both performance gains and energy savings, consistently outperforming two state-of-the-art hardware approaches.

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“…Several improvements have been proposed aimed at relaxing the release conditions in order to recycle a physical register identifier quite before the redefining instruction commits [1][2] [3][10] [15] [19] [22]. We can distinguish between safe and speculative policies.…”

Section: Introductionmentioning

confidence: 99%

“…The former takes advantage of the limited compiler knowledge in order to safely release a register read by its only consumer [15]. Any hardware approach monitors program execution so as to safely release a physical register provided that some conditions are met, such as register dependences, conditional branch outcomes or capability to raise exceptions [19] [22].…”

Section: Introductionmentioning

confidence: 99%