Hardware Platforms for Flash Memory/NVRAM Software Development

Nam, Eyee Hyun; Choi, K. S.; Choi, Jinyong; Min, Hang Jun; Min, Sang Lyul

doi:10.5626/jcse.2009.3.3.181

Cited by 5 publications

(1 citation statement)

References 11 publications

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“…Those examples are 3D clock design considering through silicon via (TSV) design variation and circuit reliability issues under the power-gated or clock-gated design environment. We hope that this survey helps to find or assess practically useful solutions to the important clock optimization problems that arise in the designs supporting diverse platforms, applications or environments (e.g., [38,39]). Fig.…”

Section: Discussionmentioning

confidence: 99%

Design Methodologies for Reliable Clock Networks

Joo¹,

Kang²,

Kim³

2012

Journal of Computing Science and Engineering

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This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

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Section: Discussionmentioning

confidence: 99%