Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic Oscillators

Bonny, Talal; Debsi, Ridhwan Al; Majzoub, Sohaib; Elwakil, Ahmed S.

doi:10.1007/s00034-018-0905-6

Cited by 40 publications

(16 citation statements)

References 26 publications

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“…The 3D-chaos based PRNG, which is itself based on Lorenz and Lu chaotic systems from [30] using the Euler method, uses the least number of resources among all systems, but offers an achievable throughput of 1872 Mbps, which is much lower than that of our proposed system. The 4D-chaos based system from [15], which is optimized for throughput, is the one that comes the closest to our system in terms of the number of LUTs, where our implementation achieves 3.6× greater throughput. The system in [31] uses the highest number of resources among all the 3D-chaos based PRNG implementations using the Euler method.…”

Section: A Comparison and Discussionmentioning

confidence: 99%

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Designing a Pseudo-Random Bit Generator with a Novel 5D-Hyperchaotic System

Nguyên¹,

Bui²,

Gagnon³

et al. 2021

Preprint

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Dynamic and non-linear systems are emerging as potential candidates for random bit generation. In this context, chaotic systems, which are both dynamic and stochastic, are particularly suitable. This paper introduces a new continuous chaotic system along with its corresponding implementation, which targets fieldprogrammable gate arrays (FPGAs). This chaotic system has five dimensions, which exhibit complex chaotic dynamics, thus enabling the utilization of chaotic signals in cryptography. A mathematical analysis is presented to demonstrate the dynamic characteristics of the proposed hyperchaotic system. A novel digital implementation of the proposed system is presented. Moreover, a data scrambling circuit is implemented to eliminate the bias effect and increase the randomness of the bitstream generated from the chaotic signals. We show that the proposed random bit generator has high randomness. The generated bits successfully pass well-known statistical randomness testsuites, i.e., NIST SP800-22, Diehard and TestU01. The readyto-use random bit generator is deployed on a Xilinx Zynq-7000 SoC ZC702 Evaluation Kit. Experimental results show that the proposed random bit generator can achieve a maximum throughput of 6.78 Gbps, which is over 3.6 times greater than state-of-the-art designs, while requiring under 4% of the resources available on the targeted FPGA.

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Section: A Comparison and Discussionmentioning

confidence: 99%

“…This means that thay have limited dynamic characteristics as the signal expands exponentially in only one direction. Speed optimization is applied to a 3D chaotic system and then expanded to a 4D chaotic system in [15], achieving a maximum throughput of 1882 Mbps for the random bit generator.…”

Section: Related Workmentioning

confidence: 99%

Designing a Pseudo-Random Bit Generator with a Novel 5D-Hyperchaotic System

Nguyên¹,

Bui²,

Gagnon³

et al. 2021

Preprint

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“…Digital signal processors that can be programmed in software are commonly used to accomplish a shared goal of system adaptability [20]. Application developers and compilers must tailor their processing approach to the computing resources available on these platforms [21], even though these platforms allow for flexible implementation due to programming interfaces.…”

Section: Introductionmentioning

confidence: 99%

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Marimuthu¹,

Rajendran²,

Radhakrishnan³

et al. 2023

Computers, Materials &Amp; Continua

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Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today's modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a fieldprogrammable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

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“…Off-system embedment weakens the security. Therefore, this is performed through digital circuits-based platforms such as hardware-based Digital Signal Processors (DSP) [18,19], Application Specific Integrated Circuits (ASIC) [20,21], and Field Programmable Gate Array (FPGA) [22,23] to remove this disadvantage. True Random Number Generators (TRNGs) are essential for cryptology and secure communication practices.…”

Section: Introductionmentioning

confidence: 99%

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

Koyuncu

Şeker²,

Alçın

et al. 2021

Balkan Journal of Electrical and Computer Engineering

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This study presents a Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized design has been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. The TRNG design has been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequencies of the TRNG in 32-bit IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard reach 344.585 MHz and 316 MHz, respectively. The throughputs of the TRNG in 32-bit IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard have been obtained as 344 Mbit/s and 316 Mbit/s, respectively. 1 Mbit sequence has been generated by using TRNG system. Randomness analysis of the generated numbers has been

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Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic Oscillators

Cited by 40 publications

References 26 publications

Designing a Pseudo-Random Bit Generator with a Novel 5D-Hyperchaotic System

Designing a Pseudo-Random Bit Generator with a Novel 5D-Hyperchaotic System

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

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