Hardware-modulated parallelism in chip multiprocessors

Abstract

Chip multi-processors (CMPs) already have widespread commercial availability, and technology roadmaps project enough on-chip transistors to replicate tens or hundreds of current processor cores. How will we express parallelism, partition applications, and schedule/place/migrate threads on these highly-parallel CMPs?This paper presents and evaluates a new approach to highly-parallel CMPs, advocating a new hardware-software contract. The software layer is encouraged to expose large amounts of multi-granular, heterogeneous parallelism. The hardware, meanwhile, is designed to offer low-overhead, low-area support for orchestrating and modulating this parallelism on CMPs at runtime. Specifically, our proposed CMP architecture consists of architectural and ISA support targeting thread creation, scheduling and context-switching, designed to facilitate effective hardware run-time mapping of threads to cores at low overheads.Dynamic modulation of parallelism provides the ability to respond to run-time variability that arises from dataset changes, memory system effects and power spikes and lulls, to name a few. It also naturally provides a long-term CMP platform with performance portability and tolerance to frequency and reliability variations across multiple CMP generations. Our simulations of a range of applications possessing do-all, streaming and recursive parallellism show speedups of 4-11.5X and energy-delay-product savings of 3.8X, on average, on a 16-core vs. a 1-core system. This is achieved with modest amounts of hardware support that allows for low overheads in thread creation, scheduling and context-switching. In particular, our simulations motivated the need for hardware support, showing that the large thread management overheads of current run-time software systems can lead to up to 6.5X slowdown. The difficulties faced in static scheduling were shown in our simulations with a static scheduling algorithm, fed with oracle profiled inputs suffering up to 107% slowdown compared to NDP's hardware scheduler, due to its inability to handle memory system variabilities. More broadly, we feel that the ideas presented here show promise for scaling to the systems expected in ten years, where the advantages of high transistor counts may be dampened by difficulties in circuit variations and reliability. These issues will make dynamic scheduling and adaptation mandatory; our proposals represent a first step towards that direction.

Analyzing and enhancing the parallel sort operation on multithreaded architectures

“…Quicksort presented in [25] outperforms the well-known parallel sample sort [4], and consumes less memory for uni and multiprocessors [24]. Chen et al [2] proposed a hardware-software module for managing threads on a 16-core simulation. They achieved speedups from 4 to 11 times for some benchmarks including qsort (the standard implementation from quicksort) compared to singlecore.…”

“…(2) Comparison sorts which depend on running comparison operations across the keys to find the correct relative order. In this work, we target both types.…”

“…Zero). (2) How the algorithm carries out the sorting (memory-intensive vs. CPU-intensive). Our results illustrate that due to the high processing load (CPU-intensive) for the radix sort; its performance gain on the Intel ® Pentium ® 4 HyperThreading (Intel's implementation from SMT) is limited by the shared execution units (resource stalls).…”

A moving threads processor architecture MTPA

“…Thread migration in distributed memory parallel computers is studied in, e.g., [10][11][12] to maximize data access locality, and thus minimize communication between the processors. In the context of chip multiprocessors, thread migration and load-balancing in general are discussed, e.g., in [13,14]. In the context of grid computing, the thread migration is studied by Chaudhary, Jiang, and Walters in [15,16].…”

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

“…The Network-Driven Processor proposed by Chen et al [10] also shares several features with CAPSULE, and its initial version called Agent Programming+SOMT [21]. They similarly propose to delegate thread creation decisions at run-time to the hardware, and show an example application on a CMP; there is also a significant development on streaming applications and support.…”