Hardware models for automated partitioning and mapping in multi-core systems

Krawczyk, Lukas; Kamsties, Erik

doi:10.1109/idaacs.2013.6663019

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…Concerning the transformation criteria, we have just five methods which are based on the metamodel such as [18], [20], [21], [24] and our proposed method. Thus, for the transformation automation, we notice some methods; use their algorithm [39] like [21], [23] and [26] while other methods transform their models relying on a transformation language; for instance, QVT for [18] and [24] or ATL in our proposal. However, we have other methods that transform their models manually relying on Human language like [14], [16] and [20].…”

Section: Discussionmentioning

confidence: 99%

An Automatic Transformation Method From the E3value Model to Uml2 Sequence Diagrams: An Mda Approach

Kharmoum¹,

Ziti²,

Rhazali³

et al. 2019

IJC

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Since the Model Driven Architecture (MDA) approach appearance, model’s transformation has been considered as one of the main computing keys in the software industry, which grows exponentially to ensure competitiveness. For that, the Object Management Group (OMG) offers for the MDA approach three abstraction levels, which are Computation Independent Model (CIM), Platform Independent Model (PIM) and Platform Specific Model (PSM). Most researchers put much focus on the PIM to PSM transformation because these levels have multiple common points, but they disregard the CIM to PIM transformation. So, our defiance in this paper is to propose a disciplined method that generates the UML2 Sequence diagrams automatically from the E3value model. Therefore, we produce the UML’s behavior and interaction model in the PIM level, from the value-based requirements model in the CIM level. The transformations are done automatically using the Atlas transformation language (ATL). The purpose is to reduce the effort, time, and the development cost of projects as all transformations is automated, increasing the chance of being more competitive in the software industry.

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Section: Discussionmentioning

confidence: 99%

An Automatic Transformation Method From the E3value Model to Uml2 Sequence Diagrams: An Mda Approach

Kharmoum¹,

Ziti²,

Rhazali³

et al. 2019

IJC

View full text Add to dashboard Cite

show abstract

“…Finally the LGP aprroach provides all system's runnables distributed among several ProcessPrototypes (user defined or automatically generated) as well as explicit CPC model elements, that can be combined and transmitted to a mapping plugin [14] for further information augmentation and finally to a code generator in order to apply the partitioning to the software and run it in parallel on a multicore system. The partitioning mechanism processes runnables (nodes) with respect to their dependencies (orderings) and execution cycles and utilizes multicore architectures by efficient parallelism and load balancing such that execution times and energy consumption can be lowered and high performance application development can be facilitated.…”

Section: Listing 1 Pseudocode For Partitioning Algorithmmentioning

confidence: 99%

Vector Clock Tracing and Model Based Partitioning for Distributed Embedded Systems

Hoettger¹,

Igel²,

Kamsties³

2014

IJC

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Tracking, partitioning and tracing in modern dynamic high performance computing systems are three of the most innovative and important development aspects for performance optimization purposes and state-of-the-art advanced quality. This paper discusses these three aspects with respect to distributed systems and proposes new mechanisms for an advanced utilization of software in this domain. We present a specific tracking mechanism via vector clocks for model and code partitioning purposes and the determination of causality relations. Further, a tracing approach for an effective analysis and thereby utilization of code and the corresponding architecture is introduced. The combination of both approaches leads to a high degree of parallelism and a fine-grained structure of execution units, that further traced, supports a precise analysis of synchronous and asynchronous system’s behavior as well as an optimal load balancing. The mechanisms are introduced with respect to a model based control engineering tool and event diagrams.

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“…Our previous publication [5] is dealing with the partitioning and mapping for heterogeneous multicore systems using a hardware model. It outlines a 2 http://blog.yakindu.org/category/damos-2/ pragmatic approach for partitioning and mapping of data flow graphs with a simple algorithm.…”

Section: Related Workmentioning

confidence: 99%

Hardware Models for Automated Partitioning and Mapping in Multi-Core Systems Using Mathematical Algorithms

Krawczyk¹,

Kamsties²

2014

IJC

Self Cite

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Multi-core CPUs offer several major benefits in embedded systems. For instance, they usually provide higher energy efficiency and more computing power compared to single-core CPUs. However, these benefits do not come for free: A program has to be divided into tasks, which can be executed in parallel on different cores. Partitioning of software and mapping on cores are nontrivial activities that require detailed knowledge about the underlying hardware platform, e.g., the number of cores, their speed, available memories, etc. Such information is typically stored in handbooks. If this information would be available in a machine readable model, we call it hardware model, the partitioning and mapping activities can be automated. In this paper, we propose a hardware model and illustrate it using an example of a Freescale multi-core CPU. We then discuss a small case study situated in the automotive domain, which illustrates the use of the hardware model in partitioning, mapping, and code generation.

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Hardware models for automated partitioning and mapping in multi-core systems

Cited by 5 publications

References 3 publications

An Automatic Transformation Method From the E3value Model to Uml2 Sequence Diagrams: An Mda Approach

An Automatic Transformation Method From the E3value Model to Uml2 Sequence Diagrams: An Mda Approach

Vector Clock Tracing and Model Based Partitioning for Distributed Embedded Systems

Hardware Models for Automated Partitioning and Mapping in Multi-Core Systems Using Mathematical Algorithms

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