Hardware (IP) Watermarking During Behavioral Synthesis

Sengupta, Anirban; Rathor, Mahendra

doi:10.1007/978-3-030-78841-4_7

Cited by 1 publication

(1 citation statement)

References 17 publications

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“…Tis is due to the well-known fact that each watermark integration method exhibits specifc latency and area overhead, and therefore, selecting an appropriate method for embedding the watermark plays a crucial role. A variety of high-level synthesis-based techniques for IP protection is well described in the literature [13][14][15][16][17][18]. For reusable IP cores, the techniques based on single-phase, triple-phase watermarking, digital signature-based watermarking, binary encoding-based watermarking, and in-synthesis-based watermarking are described.…”

Section: Introductionmentioning

confidence: 99%

Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification

Bagul¹,

Inamdar²

2023

International Journal of Reconfigurable Computing

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As the reuse of IP cores or the development of frequently used hardware modules is gaining more attention in the semiconductor industry, the misappropriation of the owner’s identity is a rising concern. Therefore, imprinting the owner’s identity in the form of a watermark or signature on the IP core is essential to avoid intellectual property right (IPR) infringement. In view of this, a watermarking technique is proposed in the present manuscript. A constraint-based dynamic watermarking method to generate the owner’s signature is proposed in conjunction with the logic encryption-based hardware obfuscation method. The method formulated in this manuscript consciously makes use of a basic switching component for embedding a watermark with IP core and hardware obfuscation, to achieve a lower overhead budget. Through the switching mechanism, the embedded watermark can be made detectable to legitimate end users off chip via test pin. The logic encryption-based method is set for accessing the watermark. Furthermore, an encrypted functionality is set as the signature generator module for generating owner’s signature. This provides hardware obfuscation and two-stage authentication mechanism for the generation of owner’s signature, and as a result of this, double-layer protection is achieved. Furthermore, a novel method to configure input key for signature generation module and to formulate owner’s signature is proposed. The viability of the present watermark technique for real-life application is checked on the ground of transparency, security, reliability, performance overhead, and robustness. Since the watermark in the proposed method is embedded outside the IP core, it does not cause any latency for the IP core functionality. Thus, even with significantly lower area overhead (∼<1.4%), the proposed method is able to provide higher robustness in terms of lower probability of coincidence (PC = 4.68 e − 97).

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