Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations

Abstract

Abstract-This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In polynomial approximations, polynomials are evaluated using stored coefficients. Polynomial interpolations, however, require the coefficients to be computed on-the-fly by using stored function values. Although it is known that interpolations require less memory than approximations, but at the expense of additional computations, the trade-offs in memory, area, delay, and power consumption between the two approaches have not been examined in detail. This work quantitatively analyzes these trade-offs for optimized approximations and interpolations across different functions and target precisions. Hardware architectures for degree-1 and degree-2 approximations and interpolations are described. The results show that the extent of memory savings realized by using interpolation is significantly lower than what is commonly believed. Furthermore, experimental results on a field-programmable gate array (FPGA) show that, for high output precision, degree-1 interpolations offer considerable area and power savings over degree-1 approximations, but similar savings are not realized when degree-2 interpolations and approximations are compared. The availability of both interpolation-based and approximation-based designs offers a richer set of design trade-offs than what is available using either interpolation or approximation alone.

<inline-formula> <tex-math notation="TeX">$(M,p,k)$</tex-math></inline-formula>-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

“…Table III first compares the estimated hardware costs of the proposed design with three different schemes, namely, the multipartite table (MTM [6]), piecewise table lookup approximation (Sasao [7]) and order-two interpolation (Lee [8]). The memory resource is counted in bit, while other supporting arithmetic/logic units are measured in the numbers of FA.…”

“…The increase in logic resources are 8.2⇥ and 1.5⇥. Because of the degree-2 interpolation algorithm adopted, the scheme of [8] can further compress the lookup tables used. However, due to the large multipliers used, the growth in logic resources is significant.…”

“…Low and Jong [2] revisited the tables-and-additions strategy and successfully proposed an integrated add-table lookup-add (iATA) approach, which could save 20% to 60% of memory compared with MTM. Other approaches, such as LUT cascades [7] and order-two piecewise polynomial approximation and interpolation approaches [8] are also studied in the literature.…”

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

“…Chebyshev polynomials provide approximations close to the optimal least-maximum approximation and can be constructed analytically. Minimax polynomials provide a better approximation, but must be computed iteratively via the Remez algorithm [33]. Neither Chebyshev nor minimax polynomials account for the combined non-linear effects of coefficient quantization errors, reduction error due to use of truncated arithmetic units and roundoff error due to rounding intermediate values.…”

Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers

“…Much work has been published on function approximation and evaluation, some of the more recent being [35][36][37]. It should be noted that the methods presented in this paper can be applied to most, if not all other designs for function approximation.…”