Hardware Implementation on FPGA for Task-Level Parallel Dataflow Execution Engine

Wang, Chao; Zhang, Junneng; Li, Xi; Wang, Aili; Zhou, Xuehai

doi:10.1109/tpds.2015.2487346

Cited by 18 publications

(5 citation statements)

References 33 publications

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“…The implementation throughput was 40 GB/s with an efficiency of 5.27 Mb/slice and a powerful performance of 286 GB/w. In [20], techniques to perform task-level out-of-order execution were proposed and implemented using the Xilinx Virtex-5 FPGA device to improve flexibility. The implementation results showed a better efficiency in terms of performance and resource usage.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

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Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quadengine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image's part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

View full text Add to dashboard Cite

show abstract

“…Refs. [9,10] propose task-level schedulers to accelerate the modules running in parallel on FPGA. HRES is a task partitioning method based on DPR (dynamic partial reconfiguration) [11].…”

Section: Heterogeneous Computing Workload Partioningmentioning

confidence: 99%

“…On the other side, task partitioning does not need to deploy FPGA resources to all sub-tasks, because part of sub-tasks entirely runs on the GPU or CPU. [9,10] propose tasklevel schedulers to accelerate the modules running in parallel on FPGA. HRES is a task partitioning method based on DPR (dynamic partial reconfiguration) [11].…”

Section: Heterogeneous Computing Workload Partioningmentioning

confidence: 99%

FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing

Wang

Zhou

2022

Electronics

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Accelerators, such as GPUs (Graphics Processing Unit) that is suitable for handling highly parallel data, and FPGA (Field Programmable Gate Array) with algorithms customized architectures, are widely adopted. The motivation is that algorithms with various parallel characteristics can efficiently map to the heterogeneous computing architecture by collaborated GPU and FPGA. However, current applications always utilize only one type of accelerator because the traditional development approaches need more support for heterogeneous processor collaboration. Therefore, a comprehensible architecture facilitates developers to employ heterogeneous computing applications. This paper proposes FLIA (Flow-Lead-In Architecture) for abstracting heterogeneous computing. FLIA implementation based on OpenCL extension supports task partition, communication, and synchronization. An embedded system of a three-dimensional waveform oscilloscope is selected as a case study. The experimental results show that the embedded heterogeneous computing achieves 21× speedup than the OpenCV baseline. Heterogeneous computing also consumes fewer FPGA resources than the pure FPGA accelerator, but their performance and energy consumption are approximate.

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“…Step 5: After receiving the Adder and Minus invoked by the user, the OS performs task scheduling to determine the dependency between the tasks and the execution timing of the tasks [15], [16], and checks whether a suitable black box can be used as an execution component. If yes, go to Step 7, otherwise go to Step 6.…”

Section: B Software Stackmentioning

confidence: 99%

A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing

et al. 2019

Self Cite

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Real-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention. The type of accelerators determines the performance of the edge computing system largely. The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios. Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs. Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency. This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform. We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency. We conduct a set of experiments on the Zynq platform to verify the proposed framework. Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude.INDEX TERMS FPGA, edge computing, task scheduling, heterogeneous system, dynamic partial reconfigurable system.

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Hardware Implementation on FPGA for Task-Level Parallel Dataflow Execution Engine

Cited by 18 publications

References 33 publications

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing

A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing

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