Hardware implementation of variable precision multiplication on FPGA

Anane, N.; Bessalah, H.; Issad, Mohamed; Messaoudi, Khadidja; Anane, M.

doi:10.1109/dtis.2009.4938028

Cited by 8 publications

(13 citation statements)

References 2 publications

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“…where t n [2], t n [1], t n [0] are the partial product bits according to binary positional weight. The product is obtained by adding s 1 , s 2 and s 3 as shown in Eq.…”

Section: Karatsuba-urdhva Tiryagbhyam Binary Multiplier For Mantissa mentioning

confidence: 99%

“…Different variable-precision floating-point methods are explained in papers [2,7,15]. A multi-mode floating-point multiplier, which operates efficiently with every precision format specified by the IEEE 754-2008 standard, is presented in paper [15].…”

mentioning

confidence: 99%

“…A model and implementation of a versatile multiplier, which can perform either double-precision (paired) or single-precision floating-point multiplications, or 16-bit or 8-bit SIMD integer (vector) multiplications, is presented in paper [7]. An efficient variable-precision floating-point multiplier design which requires very less storage area and also uses parallel additions along with multiplication is described in paper [2]. All of these studies illustrate very efficient variable-precision design methods, but run-time-reconfigurability is not the main feature of these models.…”

mentioning

confidence: 99%

“…A very good explanation of various floatingpoint formats and multiplier algorithms is given in [17]. The implementation of Karatsuba algorithm is described in papers [2,16]. A simple implementation of Karatsuba algorithm is explained in paper [16].…”

mentioning

confidence: 99%

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Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

Arish

Sharma

2016

Circuits Syst Signal Process

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In today's world, high-power computing applications such as image processing, digital signal processing, graphics, robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication. Multiplication operations require a lot of computational time and are also complex in design. We can use field-programmable gate arrays as low-cost hardware accelerators along with a low-cost general-purpose processor instead of a highcost application-specific processor for such applications. In this work, we employ an efficient Strassen's algorithm for matrix multiplication and a highly efficient run-time-reconfigurable floating-point multiplier for matrix element multiplication. The run-time-reconfigurable floating-point multiplier is implemented with custom floating-point format for variable-precision applications. A very efficient combination of Karatsuba algorithm and Urdhva Tiryagbhyam algorithm is used to implement the binary multiplier. This design can effectively adjust the power and delay requirements according to different accuracy requirements by reconfiguring itself during run time. IntroductionMatrix multiplication is the most significant operation in high-power computing applications. Multiplication operations require a lot of computational time, and the B S. Arish

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“…where t n [2], t n [1], t n [0] are the partial product bits according to binary positional weight. The product is obtained by adding s 1 , s 2 and s 3 as shown in Eq.…”

Section: Karatsuba-urdhva Tiryagbhyam Binary Multiplier For Mantissa mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

Arish

Sharma

2016

Circuits Syst Signal Process

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“…The expressions for produ p 0 a 0 b 0 p 1 1 a 1 b 0 a 0 b 1 p 2 2 MSB ADDER1 p 3 3 MSB ADDER 2 p 4 4 MSB ADDER p 5 5 MSB ADD p 6 6 MSB p 7 hyam sutra Since there are more than two operands in can use carry save addition to implement ad technique reduces the delay to a great exten ripple carry adder. Karatsuba Algorithm for multiplication Karatsuba multiplication algorithm [11,12] multiplying very large numbers. This metho Anatoli Karatsuba in 1962.…”

Section: Urdhva Tiryagbhyam Algorithmentioning

confidence: 99%

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Arish

Sharma

2015

2015 International Conference on Signal Processing and Communication (ICSC)

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Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

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Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Tomar¹,

George

Tomar

2021

IET Circuits, Devices & Syst

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Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating-point multiplication is an important component. The dynamic range of numbers represented by floating-point arithmetic is very large compared with that of fixed-point numbers of the same bit width. A mantissa similarity investigator (MSI)interfaced multi-precision binary multiplier architecture is developed and can be used in data-intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single-, double-, quadruple-and octuple-precision modes for mantissa multiplication according to the IEEE 754 standard for floating-point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field-programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Hardware implementation of variable precision multiplication on FPGA

Cited by 8 publications

References 2 publications

Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

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