Hardware implementation of shortened (48,38) reed solomon forward error correcting code

Khan, Mubashar; Afzal, Shiraz; Manzoor, Rizwan

doi:10.1109/inmic.2003.1416621

Cited by 9 publications

(3 citation statements)

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“…With the compliance to existing IEEE 802.11n MAC frame structure, the proposed FEC mechanism is constructed according to the RS code [24,25] that is well-adopted in the design of outer decoders. The coefficients of generator polynomial G(x) are elements in a finite field GFð2 n b Þ, where n b = 8 is chosen according to the byte-oriented system.…”

Section: Fec Mechanism Of Ah-arq Schemementioning

confidence: 99%

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Design of MAC-defined aggregated ARQ schemes for IEEE 802.11n networks

2010

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Based on the IEEE 802.11n standard, frame aggregation is considered one of the major factors to improve system performance of wireless local area networks (WLANs) from the medium access control (MAC) perspective. In order to fulfill the requirements of high throughput performance, feasible design of automatic repeat request (ARQ) mechanisms becomes important for providing reliable data transmission. In this paper, two MAC-defined ARQ schemes are proposed to consider the effect of frame aggregation for the enhancement of network throughput. An aggregated selective repeat ARQ (ASR-ARQ) algorithm is proposed, which incorporates the conventional selective repeat ARQ scheme with the consideration of frame aggregation. On the other hand, the aggregated hybrid ARQ (AH-ARQ) protocol is proposed to further enhance throughput performance by adopting the Reed-Solomon block code as the forward error correction (FEC) scheme. Novel analytical models based on the signal flow graph are established in order to realize the retransmission behaviors of both schemes. Simulations are conducted to validate and compare the proposed ARQ mechanisms with existing schemes based on service time distribution. Numerical results show that the proposed AH-ARQ protocol outperforms the other retransmission schemes owing to its effective utilization of FEC mechanism.

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Section: Fec Mechanism Of Ah-arq Schemementioning

confidence: 99%

“…The proposed AH-ARQ scheme can be categorized as type-I of H-ARQ algorithm, which is served as an outer code designed from the MAC layer perspective. The Reed-Solomon (RS) code [24,25], which defines a finite codeword length, is adopted within the AH-ARQ scheme.…”

Section: Introductionmentioning

confidence: 99%

Design of MAC-defined aggregated ARQ schemes for IEEE 802.11n networks

2010

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“…Authors in [21] proposed efficient hardware implementation of BCH code. Further, hardware implementation of non-binary BCH code or RS code is also proposed by authors in [22]. The basic building blocks of error correcting code is the finite field arithmetic.…”

Section: Introductionmentioning

confidence: 99%

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code

Mandal¹,

Tavva

Bhattacharjee

et al. 2019

VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

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Error resilient high speed robust data communication is the primary need in the age of big data and Internet-of-things (IoT), where multiple connected devices exchange huge amount of information. Different multi-bit error detecting and correcting codes are used for error mitigation in the high speed data communication though it introduces delay and their decoding structures are quite complex. Here we have discussed the implementation of single bit error correcting Bose, Chaudhuri, Hocquenghem (BCH) code with simple decoding structure on a state-of-the art ReRAM based in-memory computing platform. ReRAM devices offer low leakage power, high endurance and non-volatile storage capabilities, coupled with stateful logic operations. The proposed lightweight library presents the mapping for generation of elements on Galois field (GF ) for computation of BCH code, along with encoding and decoding operations on input data stream using BCH code. We have verified the results for BCH code with different dimensions using SPICE simulation. For (15,11) BCH code, the number of clock cycles required for element generation, decoding and encoding of BCH code are 103, 230 and 251 respectively, which demonstrates the efficacy of the mapping.

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A novel method for performance improvement of optical CDMA system using alterable concatenated code

Qiu

Zhang

2007

Optics Communications

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Hardware implementation of shortened (48,38) reed solomon forward error correcting code

Cited by 9 publications

References 1 publication

Design of MAC-defined aggregated ARQ schemes for IEEE 802.11n networks

Design of MAC-defined aggregated ARQ schemes for IEEE 802.11n networks

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code

A novel method for performance improvement of optical CDMA system using alterable concatenated code

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