Hardware implementation of PSO-based approximate DST transform for VVC standard

Jdidia, Sonda Ben; Belghith, Fatma; Sallem, Amin; Jridi, Maher; Nouri, Mohammad

doi:10.1007/s11554-021-01160-5

Cited by 2 publications

(6 citation statements)

References 28 publications

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“…This can be achieved by efficiently implementing either the exact or the approximate version of the transform. A fairly relevant approximation of the DST-VII transform was proposed in [ 10 ] which targets the transforms of sizes 8, 16, and 32. The hardware architectures of both exact and approximate 1D transforms were designed.…”

Section: Vvc Transformmentioning

confidence: 99%

“…The hardware architectures of both exact and approximate 1D transforms were designed. This paper focuses on the 2D implementation of the DST-VII transform in its exact and approximate versions based on the 1D architecture of [ 10 ].…”

Section: Vvc Transformmentioning

confidence: 99%

“…The hardware synthesis results show that the approximate design presents 70% of hardware resources saving with regard to the exact transform implementation. Ben Jdidia et al [ 10 ] proposed a hardware description of 8- and 16-point exact transforms using multipliers and the Multiple Constant Multiplication (MCM) algorithm as well as the approximate transforms using addition and bit-shifting operations. The synthesis results reveal that the proposed approximations provide a significant gain in terms of hardware resources and power consumption.…”

Section: Vvc Transformmentioning

confidence: 99%

“…Duplicating the 1D transforms can be needed to pipeline all the computation, at the cost of a higher area usage. The proposed architecture is based on the 1D DST-VII design of [ 10 ] to compute either the exact or the approximate version of the DST-VII transform. Since the design is unified for sizes 8, 16 and 32, then, according to the “ ” signal which defines the transform size to be used in the 1D transform, the input column is given in one cycle when the transform size is 8, two cycles when the transform size is 16 (first half first) and four cycles when the transform size is 32 (first quarter first).…”

Section: D Dst-vii Transform Hardware Implementationmentioning

confidence: 99%

“…For a given input column vector X_N which is an bit vector, one of the mentioned methods is used to compute the ouput Y_N whose width depends on the computation method. The three methods are well explained in [ 10 ].…”

Section: D Dst-vii Transform Hardware Implementationmentioning

confidence: 99%

See 4 more Smart Citations

A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard

Jdidia

Belghith

Nouri

2022

J Real-Time Image Proc

Self Cite

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The versatile video coding standard H.266/VVC release has been accompanied with various new contributions to improve the coding efficiency beyond the high-efficiency video coding (HEVC), particularly in the transformation process. The adaptive multiple transform (AMT) is one of the new tools that was introduced in the transform module. It involves five transform types from the discrete cosine transform/discrete sine transform families with larger block sizes. The DCT-II has a fast computing algorithm, while the DST-VII relies on a complex matrix multiplication. This has led to an additional computational complexity. The approximation of the DST-VII can be used for the transform optimization. At the hardware level, this method can provide a gain in power consumption, logic resources use and speed. In this paper, a unifed two-dimensional transform architecture that enables exact and approximate DST-VII computation of sizes and is proposed. The exact transform computation can be processed using either multipliers or the MCM algorithm, while the approximate transform computation is based on additions and bit-shifting operations. All the designs are implemented under the Arria 10 FPGA device. The synthesis results show that the proposed design implementing the approximate transform matrices is the most efficient method with only 4% of area consumption. It reduces the logic utilization by more than 65% compared to the multipliers-based exact transform design, while about 53% of hardware cost saving is obtained when compared to the MCM-based computation. Furthermore, the approximate-based 2D transform architecture can operate at 78 MHz allowing a real-time coding for 2K and 4K videos at 100 and 25 frames/s, respectively.

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Section: Vvc Transformmentioning

confidence: 99%

Section: Vvc Transformmentioning

confidence: 99%

Section: Vvc Transformmentioning

confidence: 99%

Section: D Dst-vii Transform Hardware Implementationmentioning

confidence: 99%

Section: D Dst-vii Transform Hardware Implementationmentioning

confidence: 99%

See 3 more Smart Citations

A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard

Jdidia

Belghith

Nouri

2022

J Real-Time Image Proc

Self Cite

View full text Add to dashboard Cite

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FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

Wu,

Zhang,

Zhang

2024

Energies

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To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

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Hardware implementation of PSO-based approximate DST transform for VVC standard

Cited by 2 publications

References 28 publications

A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard

A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

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