Hardware Implementation of High-Throughput S-Box in AES for Information Security

Abstract

The Advanced Encryption Standard (AES) is used for achieving quantum-resistant cryptography when a 256-bit key is applied. This paper presents a high-throughput, seven-stage hardware pipeline architecture for SubByte computations in the AES for information security applications. Composite field arithmetic-based calculations are employed for logic optimization. The proposed architecture includes dedicated multistage multiplication processes based on Galois field polynomials for constants, squaring, and variables; thus, the critical path of SubByte computations is shortened, and the maximum operating frequency is enhanced. The proposed architecture was synthesized using a TSMC 40-nm cell library, and the throughput of the proposed architecture (34.78 Gbps) was observed to be superior to that of an existing state-of-the-art architecture by 43.47%. Moreover, our architecture was noted to consume lower dynamic power for combinational logic circuits, indicating that the proposed architecture has greater computational logic optimization than existing designs. The proposed architecture is feasible for communication security applications in the Internet of Things systems because of its high throughput and area efficiency.INDEX TERMS AES, hardware, high-throughput, information security, S-box.NARN-YIH LEE received the Ph.D. degree in information engineering from the National Cheng Kung University, Taiwan, in 1996. He is currently a Professor with the Computer and Network Center, National Cheng Kung University. His research interests include cryptography, blockchain, network security, post quantum cryptography, and chip security.

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

“…The integration of emerging devices with the latest technologies represents a transformative phase in the realm of electronics. This process involves seamlessly incorporating innovative components like memristors, spintronic devices, and quantum devices [333] into existing systems. One of the primary challenges lies in ensuring compatibility and establishing standardized interfaces for the smooth integration of these emerging technologies.…”

“…On one hand, the advent of powerful quantum computers raises concerns about their capability to break widely-used cryptographic algorithms, rendering current security protocols vulnerable [333]. On the other hand, quantum principles also offer potential solutions for enhancing hardware security.…”