Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes

This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8$$\times$$ × improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24$$\times$$ × improvement in throughput over a baseline serial decoder.

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Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

Srivastava

Gaudet

Mitran

2022

J Sign Process Syst

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Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes

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Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

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